US3959587A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Device for synchronizing a receiver of numerical data
Assignee: Alcatel CIT SA
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Filing: 1973-07-06
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Granted: 1976-05-25
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Expires: 1993-07-06
Abstract
Abstract Device for synchronizing a receiver of digital data which serves to identify the beginning of the coding word, for example a level received, hence attributing to each pulse a correct weight in a manner such as to confer on each sample received an amplitude corresponding exactly to the amplitude of the sample taken at the emission, or more generally, for attributing to each pulse a content of data corresponding to the coding at the emission, for example the primary color in a trichromatic color transmission.
Inventors
- 👤 Bernard Allias
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 22:06
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/04; H04L7/08; H04L7/041; H04L7/046; H04L7/044
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
168 words
A device for the synchronization of a received transmission of successive messages formed by coded pulses of 1 bits including a synchronization bit k for each message, comprising a counter having a capacity of q bits connected to count the coded pulses of said received transmission, said counter being capable of being preset to a selected count, decoder means connected to the output of said counter for providing a clock signal upon detection of each count k of each successive message, error detector means connected to receive said clock signal and said transmission of coded pulses for generating an error signal upon detection of an error in the value of said synchronization bit, presetting means responsive to the output of said error detector means for presetting said counter to said selected count in the case of detection of an error in the value of said synchronization bit by said error detector means, and output means for transmitting said successive messages of coded pulses in synchronism with said counter.
Claim 2
Independent Claim
168 words
A device for the synchronization of a received transmission of successive messages formed by coded pulses of 1 bits including a synchronization bit k for each message, comprising a counter having a capacity of q bits connected to count the coded pulses of said received transmission, said counter being capable of being preset to a selected count, decoder means connected to the output of said counter for providing a clock signal upon detection of each count k of each successive message, error detector means connected to receive said clock signal and said transmission of coded pulses for generating an error signal upon detection of an error in the value of said synchronization bit, presetting means responsive to the output of said error detector means for presetting said counter to said selected count in the case of detection of an error in the value of said synchronization bit by said error detector means, and output means for transmitting said successive messages of coded pulses in synchronism with said counter.
Claim 3
Dependent Claim
14 words
A device according to claim 1, wherein said selected count is k - 1.
Claim 4
Dependent Claim
24 words
A device according to claim 1, further including accumulator means for storing error signals connected between said error detector means and said presetting means.
Claim 5
Dependent Claim
58 words
A device according to claim 1, wherein the synchronizing bit alternates in valency from one message to the following message, said error detector means being provided in the form of maans for detecting identity between successive synchronization bits comprising two flip-flop connected in series and an EXCLUSIVE OR circuit connected to the outputs of said two bistable flip-flops.
Claim 6
Dependent Claim
28 words
A device according to claim 1, further including output control means for inhibiting said output means in response to detection of an output from said error detector means.
Claim 7
Dependent Claim
39 words
A device according to claim 3, wherein said accumulator means includes logic means for enabling said presetting means upon detecting three successive error signals and for disabling said presetting means upon detection of two successive absences of error signals.
Claim 8
Dependent Claim
87 words
A device according to claim 3, wherein said accumulator means comprises a shift register connected to the output of said error detector means, first gate means connected to said shift register to detect three successive error signals stored therein, second gate means connected to said shift register to detect three successive error signals followed by absence of an error signal and a fourth error signal, and third gate means for applying the outputs of said first and second gate means to said presetting means in control thereof.
Claim 9
Dependent Claim
79 words
A device according to claim 4, wherein said flip-flops forming part of said error detector means are of the D-type having D and C inputs and Q and Q outputs, the D input of one flip-flop receiving said transmission and the C input of both flip-flops receiving said clock signal, the Q output of said one flip-flop being connected to the D input of the other flip-flop, the outputs of both flip-flops being connected to said EXCLUSIVE OR circuit.
Claim 10
Dependent Claim
68 words
A devie according to claim 7, wherein said shift register comprises five flip-flops of the D-type having Q and Q outputs, said first gate means comprises one AND gate receiving the Q outputs of the first three stages and the Q output of the fourth stage and said second gate means comprises a second AND gate receiving the Q outputs of the first and third through fifth stages.
Claim 11
Dependent Claim
28 words
A device according to claim 7, further including output control means for inhibiting said output means in response to detection of an output from said third gate means.
Claim 12
Independent Claim
196 words
A device for the synchronization of a received transmission formed by a sequence of binary pulses arranged in message blocks of q bits and containing in a particular location inside each block a predetermined synchronization bit, comprising: a counter of a capacity of q bits and having a count input, a set input by which the counter is set to a first predetermined count and output terminals, a clock pulse generator producing clock pulses in synchronism with the received transmission and feeding these clock pulses to the count input of the counter, decoder means connected to the output terminals of said counter for providing a signal upon detection of a second predetermined count which differs from said first predetermined count, output means for distributing said received transmission into successive block in synchronism with said counter, error detector means receiving said received transmission in response to the output of said decoder for enabling the set input of said counter upon detection of lack of correspondance of the received bit to said predetermined synchronization bit, and means for inhibiting said output means in response to the output of said error detector upon detection of said lack of correspondance.
Claim 13
Independent Claim
196 words
A device for the synchronization of a received transmission formed by a sequence of binary pulses arranged in message blocks of q bits and containing in a particular location inside each block a predetermined synchronization bit, comprising: a counter of a capacity of q bits and having a count input, a set input by which the counter is set to a first predetermined count and output terminals, a clock pulse generator producing clock pulses in synchronism with the received transmission and feeding these clock pulses to the count input of the counter, decoder means connected to the output terminals of said counter for providing a signal upon detection of a second predetermined count which differs from said first predetermined count, output means for distributing said received transmission into successive block in synchronism with said counter, error detector means receiving said received transmission in response to the output of said decoder for enabling the set input of said counter upon detection of lack of correspondance of the received bit to said predetermined synchronization bit, and means for inhibiting said output means in response to the output of said error detector upon detection of said lack of correspondance.
Claim 14
Dependent Claim
23 words
A device according to claim 11, further including accumulator means for storing error conditions connected between said error detector means and said counter.
Claim 15
Dependent Claim
58 words
A device according to claim 11, wherein the synchronizing bit alternates in valency from one message to the following message, said error detector means being provided in the form of means for detecting identity between successive synchronization bits comprising two flip-flops connected in series and an EXCLUSIVE OR circuit connected to the outputs of said two bistable flip-flops.
Claim 16
Dependent Claim
58 words
A device according to claim 11, in which the counter is provided with at least two set inputs by which the counter is set to different predetermined counts and in which the activation of one particular set input is selected by a commutator controlled according to the sequence of a channel to be decoded within a multiplex frame.
Claim 17
Dependent Claim
39 words
A device according to claim 1, wherein said accumulator means includes logic means for enabling said presetting means upon detecting three successive error signals, and for disabling said presetting means upon detection of two successive absences of error signals.
Claim 18
Dependent Claim
87 words
A device according to claim 12, wherein said accumulator means comprises a shift register connected to the output of said error detector means, first gate means connected to said shift register to detect three successive error signals stored therein, second gate means connected to said shift register to detect three successive error signals followed by absence of an error signal and a fourth error signal, and third gate means for applying the outputs of said first and second gate means to said set input of said counter.
Claim 19
Dependent Claim
68 words
A device according to claim 16, wherein said shift register comprises five flip-flops of the D-type having Q and Q outputs, said first gate means comprises one AND gate receiving the Q outputs of the frist three stages and the Q output of the fourth stage and said second gate means comprises a second AND gate receiving the Q outputs of the first and third through fifth stages.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-05-25 | 1979-11-24 | 1980-05-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-05-25 | 1983-11-24 | 1984-05-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-05-25 | 1987-11-24 | 1988-05-25 | $7700.00 | Window Closed / Lapsed |