US3962590A
Expired / Lapsed
US
⏱️ 0.0 years remaining
TTL compatible logic gate circuit
Assignee: AT&T Inc
•
Filing: 1974-08-14
•
Granted: 1976-06-08
•
Expires: 1994-08-14
Abstract
Abstract A logic gate circuit includes a resistance divider input to the base of an input transistor and a multiple emitter output transistor in an emitter follower configuration. The circuit has favorable switching speed and power dissipation characteristics and reduces the effect of both capacitive loading and series resistance in signal interconnections. An efficient layout of one such logic circuit has intercell wiring channels formed across the circuit and has the inputs and outputs of the circuit arranged in two lines each of which crosses perpendicular to the wiring channels.
Inventors
- 👤 Jack Kane
- 👤 Richard Alan Pedersen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 14:27
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/018; H03K19/01806; H03K19/02; H03K19/08; H03K19/082; H03K19/088; H10; H10D; H10D84/00; H10D84/60; H10D84/611; H10D84/613; Y; Y10; Y10S; Y10S148/00; Y10S148/136
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
157 words
A two transistor logic gate circuit comprising: an input terminal and a plurality of output terminals, an input transistor having the emitter connected to a first bias terminal, and a first Schottky barrier diode connected between the base and collector, the collector being connected to a second bias terminal through a series combination comprising a second Schottky barrier diode, a first resistor, and a second resistor; an input resistance divider having a first terminal node connected to said input terminal for receiving an input signal, a second terminal node connected to said first bias terminal, and an intermediate node connected to the base of said input transistor; and a multi-emitter output transistor connected in an emitter follower configuration having the base connected to said series combination at a node between said first and second resistors, the collector connected to said second bias terminal, and each emitter connected to a different one of said plurality of output terminals.
Claim 2
Dependent Claim
157 words
A two transistor logic gate circuit comprising: an input terminal and a plurality of output terminals, an input transistor having the emitter connected to a first bias terminal, and a first Schottky barrier diode connected between the base and collector, the collector being connected to a second bias terminal through a series combination comprising a second Schottky barrier diode, a first resistor, and a second resistor; an input resistance divider having a first terminal node connected to said input terminal for receiving an input signal, a second terminal node connected to said first bias terminal, and an intermediate node connected to the base of said input transistor; and a multi-emitter output transistor connected in an emitter follower configuration having the base connected to said series combination at a node between said first and second resistors, the collector connected to said second bias terminal, and each emitter connected to a different one of said plurality of output terminals.
Claim 3
Dependent Claim
42 words
A logic circuit as recited in claim 1 wherein the parameters of the first and second Schottky barrier diodes are chosen so the voltage across the first Schottky barrier diode is about equal to the voltage across the second Schottky barrier diode.
Claim 4
Dependent Claim
44 words
A logic circuit as recited in claim 1 wherein the ratio of the resistance between the two terminal nodes of the input resistance divider and the resistance between the intermediate node and the second terminal node of the input resistance divider is about 1.5.
Claim 5
Dependent Claim
37 words
A logic circuit as recited in claim 1 wherein a voltage source is connected to said second bias terminal for applying thereto a voltage whose magnitude is approximately three times the base-emitter voltage of the input transistor.
Claim 6
Dependent Claim
43 words
A logic circuit as recited in claim 1 wherein the circuit parameters of the input and output transistors are such that the magnitude of the base-emitter voltage of the input transistor about equals the magnitude of the base-emitter voltage of the output transistor.
Claim 7
Dependent Claim
234 words
A two transistor logic gate circuit comprising: an input transistor having a Schottky-clamp diode connected between the base and the collector, and having the emitter connected to ground, an input resistance divider having a first terminal node for receiving an input signal, a second terminal node connected to ground, and an intermediate node connected to the base of the input transistor wherein the ratio of the resistance between the two terminal nodes of the input resistance divider and the resistance between the intermediate node and the second terminal node of the input resistance divider is about 1.5, a series combination including a Schottky barrier diode, a first resistor, and a second resistor connected between the collector of the input transistor and a voltage source wherein the parameters of the diodes are chosen so that the voltage across the Schottky-clamp diode is about equal to the voltage across the Schottky barrier diode, and an output transistor having multiple emitters and connected in an emitter-follower configuration such that its base is connected to a node between the first and the second resistor, its collector being connected to said voltage source and each emitter of the output transistor being connected to an output node, wherein the circuit parameters of the output transistor are such that the magnitude of the base-emitter voltage of the output transistor about equals the magnitude of the base-emitter voltage of the input transistor.
Claim 8
Dependent Claim
234 words
A two transistor logic gate circuit comprising: an input transistor having a Schottky-clamp diode connected between the base and the collector, and having the emitter connected to ground, an input resistance divider having a first terminal node for receiving an input signal, a second terminal node connected to ground, and an intermediate node connected to the base of the input transistor wherein the ratio of the resistance between the two terminal nodes of the input resistance divider and the resistance between the intermediate node and the second terminal node of the input resistance divider is about 1.5, a series combination including a Schottky barrier diode, a first resistor, and a second resistor connected between the collector of the input transistor and a voltage source wherein the parameters of the diodes are chosen so that the voltage across the Schottky-clamp diode is about equal to the voltage across the Schottky barrier diode, and an output transistor having multiple emitters and connected in an emitter-follower configuration such that its base is connected to a node between the first and the second resistor, its collector being connected to said voltage source and each emitter of the output transistor being connected to an output node, wherein the circuit parameters of the output transistor are such that the magnitude of the base-emitter voltage of the output transistor about equals the magnitude of the base-emitter voltage of the input transistor.
Claim 9
Dependent Claim
27 words
A logic gate circuit as recited in claim 6 wherein the magnitude of the voltage source is approximately three times the base-emitter voltage of the input transistor.
References Cited (Backward Citations)
US3218483A
Cited
US3518458A
Cited
US3623925A
Cited
US3660676A
Cited
US3699362A
Cited
US3860830A
Cited
US3769524A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-06-08 | 1979-12-08 | 1980-06-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-06-08 | 1983-12-08 | 1984-06-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-06-08 | 1987-12-08 | 1988-06-08 | $7700.00 | Window Closed / Lapsed |