Analog rate changer

Claim 2

An analog rate changer comprising: an input for receiving analog signals bearing information of which the frequencies thereof are a part; an A/D converter for converting the analog input signals to corresponding digital signals; a plurality of fall-through registers for storing the digital signals from said A/D converter; write control means for successively entering the digital signals into the plurality of registers, the digital signals being entered into each register at a write rate, said write control means including means responsive to each register in the succession becoming filled to storage capacity with digital signals for terminating entry of digital signals thereinto, and means responsive to each register in the succession becoming filled to storage capacity with digital signals for initiating entry of digital signals to the next register in the succession; read control means for continuously removing from all of the plurality of fall-through registers the digital signals stored therein, the stored digital signals being removed from said registers at a read rate less than said write rate; and means for converting the digital signals from the plurality of registers to corresponding analog output signals, said analog output signals bearing information substantially duplicative of that carried by the corresponding analog input signals and having frequencies proportionately less than the analog input signals corresponding thereto.

Claim 3

The analog rate changer of claim 1 including reset means responsive to each register being filled to storage capacity for generating a reset pulse coupled to the next register in the succession, each of said fall-through registers being cleared of any digital signal stored therein in response to a reset pulse being coupled thereto.

Claim 4

The analog rate changer of claim 2 including means for proportionately varying together said write rate and said read rate whereby the ratio of the write rate to the read rate may be maintained at a constant value while the absolute values of the rates are changed.

Claim 5

The analog rate changer of claim 3 including means for manually selecting said ratio, said proportionately varying means being operable to vary the absolute value of the write rate and the read rate while maintaining said selected ratio.

Claim 6

The analog rate changer of claim 3 in which said write control means includes means for generating periodic write command pulses at a frequency which establishes said write rate, said read control means includes means for generating periodic read command pulses at a frequency which establishes said read rate, and said proportionately varying means includes means for generating a clock signal, means for varying the frequency of the clock signal, and means for synchronizing generation of both said write command pulses and said read command pulses with said clock signal.

Claim 7

The analog rate changer of claim 5 in which said A/D converter samples successive time segments of said analog input signals and converts each of said sample segments to a representative digital signal at a rate proportional to the frequency of said clock signal.

Claim 8

The analog rate changer of claim 6 in which the digital signals are presented at an output means of the A/D converter and each digital signal being presented when a write command pulse is being generated is clocked into the one register in which the digital signals are being entered, and said write command pulse generating means generates said pulses at a rate less than that at which the digital signals are presented whereby less than all of the digital signals presented are entered into the register.

Claim 9

The analog rate changer of claim 7 including means for varying the ratio of the write command pulse frequency to the read command pulse frequency and means for varying the proportion of digital signals from the A/D converter that are clocked into a register in inverse relationship to the variation of said ratio.

Claim 10

The analog rate changer of claim 6 in which said A/D converter generates a conversion complete pulse when each digital signal is presented, and said synchronizing means includes a binary counter driven by said conversion complete pulses and having multiple outputs each generating output pulses at a different half multiple frequency of the conversion complete pulse frequency, said write command pulse generating means being responsive to the puses from a selected one of said binary counter outputs for generating said write pulses and said read command pulse generating means being responsive to the pulses from another selected one of said binary counter outputs for generating said read command pulse.

Claim 11

The analog rate changer of claim 2 in which said write control means includes means associated with each register for generating when enabled a periodic write command pulse at a frequency establishing said write rate, a digital signal being entered into a register only in response to a write command pulse from the associated write command pulse generating means, said terminating means includes means responsive to a register becoming filled to storage capacity for disabling the write command pulse generating means associated therewith, and said initiating means includes means responsive to one of said fall-through registers becoming filled for enabling the write command pulse generating means associated with the next fall-through register of the succession.

Claim 12

The analog rate changer of claim 10 in which said plurality of registers are two registers and said write control means includes a bistable multivibrator, said bistable multivibrator assuming one state in response to one of said two registers becoming filled to storage capacity and assuming a second state in response to the other register becoming filled to storage capacity, said terminating means including means for disabling the write command pulse generating means associated with the one fall-through register when the bistable multivibrator is in said one state, and disabling the write command pulse generating means associated with the other fall-through register when the bistable multivibrator is in said second state.

Claim 13

The analog rate changer of claim 11 in which said reset means includes means to clear the one fall-through register in response to said bistable multivibrator switching to said second state and means to clear the other fall-through register in response to said bistable multivibrator switching to one state.

Claim 14

The analog rate changer of claim 2 in which said plurality of fall-through registers are two fall-through registers, and said initiating means alternately initiates entry of the digital signals into the fall-through registers and said terminating means alternately terminates entry of digital signals into the two fall-through registers.

Claim 15

The analog rate changer of claim 2 including means for mixing the analog output signal from each of the plurality of registers into a single signal.

Claim 16

An analog rate changer comprising: an input for receiving analog input signals bearing information of which the frequencies thereof are a part; an A/D converter for converting the analog input signals to corresponding digital signals; a pair of fall-through registers for storing the digital signals; write control means for continuously entering the digital signals into both of the fall-through registers, said digital signals being entered into said fall-through registers at a write rate; read control means for alternately removing the stored digital signals from the two registers, said stored digital signals being removed from each register at a read rate greater than said write rate, said read control means including means responsive to each of the fall-through registers becoming filled to storage capacity with digital signals for initiating removal of the digital signals therefrom and for terminating the removal of digital signals from the other register; and means for converting the digital signals removed from the two registers to analog output signals, said analog output signals bearing information substantially duplicative of that carried by said analog input signals corresponding thereto and having frequencies proportionately greater than the analog input signals corresponding thereto.

Claim 17

An analog rate changer comprising: an input for receiving analog input signals bearing information of which the frequencies thereof are a part; an A/D converter for converting the analog input signals to corresponding digital signals; a pair of fall-through registers for storing the digital signals; write control means for continuously entering the digital signals into both of the fall-through registers, said digital signals being entered into said fall-through registers at a write rate; read control means for alternately removing the stored digital signals from the two registers, said stored digital signals being removed from each register at a read rate greater than said write rate, said read control means including means responsive to each of the fall-through registers becoming filled to storage capacity with digital signals for initiating removal of the digital signals therefrom and for terminating the removal of digital signals from the other register; and means for converting the digital signals removed from the two registers to analog output signals, said analog output signals bearing information substantially duplicative of that carried by said analog input signals corresponding thereto and having frequencies proportionately greater than the analog input signals corresponding thereto.

Claim 18

The analog rate changer of claim 15 including reset means responsive to each register being filled to storage capacity for clearing the other register of any digital signals sotred therein.

Claim 19

The analog rate changer of claim 16 including means for proportionately varying together said write rate and said read rate.

Claim 20

The analog rate changer of claim 17 in which said write control means includes means for generating periodic write command pulses at a frequency which establishes said write rate, said read control means includes means for generating periodic read command pulses at a frequency which establishes said read rate, and said proportional varying means includes means for generating a clock signal, means for varying the frequency of the clock signal, and means for synchronizing generation of both said write command pulses and said read command pulses with said clock signal.

Claim 21

The analog rate changer of claim 18 in which said A/D converter samples successive time segments of said analog input signal and converts each of said sample segments into a representative digital signal at a rate porportional to the frequency of said clock signal whereby said sampling rate may be varied by varying said clock signal while maintaining the ratio of the read rate to the write rate at a constant value.

Claim 22

The analog rate changer of claim 19 in which the digital signals are presented at an output means of the A/D converter and each digital signal being presented when a write command pulse is generated is clocked into both of the registers, and said write command pulse generating means generates said pulses at a rate less than that at which the digital signals are presented whereby less than all of the digital signals presented are entered into the registers.

Claim 23

The analog rate changer of claim 19 including means for generating a periodic clock pulse, and manually operable switch means having one state in which said read command pulses are generated at a frequency porportional to that of the frequency of said clock pulse and another state in which said read command pulses are generated at a frequency which is synchronized with said clock signal of the proportional bearing means.

Claim 24

The analog rate changer of claim 15 including means for mixing together the analog output signals from the two registers to form a single output signal.

Claim 25

An analog rate changer comprising: an input for receiving analog input signals bearing information of which the frequencies thereof are a part; an A/D converter for converting the analog input signals to corresponding digital signals; a pair of fall-through registers for storing the digital signals from said A/D converter, said fall-through registers receiving said digital signals at input means thereof and providing stored digital signals at output means thereof; means for converting the digital signals provided at the respective output means of said pair of fall-through registers into corresponding analog output signals; time contraction means for controlling the input and output of said pair of fall-through registers to develop an analog output signal corresponding to but having a lower frequency spectrum than said analog input signals including first write control means for alternately entering the digital signals into the pair of fall-through registers at a write rate, said digital signals being enetered into each register until the other fall-through register is filled to storage capacity with digital signals, and first read control means for simultaneously removing data from both of said registers at a first read rate less than said first write rate; time expansion means for controlling the respective inputs and outputs of said pair of fall-through registers to develop analog output signals corresponding to but having a lower frequency spectrum than said analog input signals, including second write control means for continuously entering the digital signals into both of said pair of fall-through registers at a second write rate, and second read control means for alternately removing the stored digital signals in said pair of fall-through registers, said digital signals being removed from said registers at a second read rate greater than said second write rate, digital signals being removed from each register until the other one of the pair of fall-through registers has been filled to storage capacity with digital signals; and switch means for selectively rendering operative one of said time contraction means and said time expansion means.

Claim 26

An analog rate changer comprising: an input for receiving analog input signals bearing information of which the frequencies thereof are a part; an A/D converter for converting the analog input signals to corresponding digital signals; a pair of fall-through registers for storing the digital signals from said A/D converter, said fall-through registers receiving said digital signals at input means thereof and providing stored digital signals at output means thereof; means for converting the digital signals provided at the respective output means of said pair of fall-through registers into corresponding analog output signals; time contraction means for controlling the input and output of said pair of fall-through registers to develop an analog output signal corresponding to but having a lower frequency spectrum than said analog input signals including first write control means for alternately entering the digital signals into the pair of fall-through registers at a write rate, said digital signals being enetered into each register until the other fall-through register is filled to storage capacity with digital signals, and first read control means for simultaneously removing data from both of said registers at a first read rate less than said first write rate; time expansion means for controlling the respective inputs and outputs of said pair of fall-through registers to develop analog output signals corresponding to but having a lower frequency spectrum than said analog input signals, including second write control means for continuously entering the digital signals into both of said pair of fall-through registers at a second write rate, and second read control means for alternately removing the stored digital signals in said pair of fall-through registers, said digital signals being removed from said registers at a second read rate greater than said second write rate, digital signals being removed from each register until the other one of the pair of fall-through registers has been filled to storage capacity with digital signals; and switch means for selectively rendering operative one of said time contraction means and said time expansion means.

Claim 27

The analog rate changer of claim 23 in which both of said time contraction and time expansion means include reset means responsive to one of said pair of fall-through registers becoming filled to storage capacity with digital signals to clear the other of said pair of fall-through registers of any digital signals stored therein.

Claim 28

An analog rate changer comprising: an input for receiving analog signals bearing information of which the frequencies thereof are a part; an A/D converter for converting the analog input signals to corresponding digital signals at a conversion sampling rate; a memory for storing the digital signals from the A/D converter; means for clocking the digital signals into the register at one rate; means for clocking stored digital signals out of the memory at another rate different from said one rate; means for synchronizing both the one rate and the other rate with the conversion sampling rate of the A/D converter; means for varying the sampling rate of the A/D converter; and means for reducing the one rate relative to the other rate by reducing the one rate relative to the conversion sampling rate whereby the proportion of digital signals developed by the A/D converter which are clocked into the memory is reduced as the ratio of the one rate to the other rate is reduced.

Claim 29

An analog rate changer comprising: an input for receiving analog signals bearing information of which the frequencies thereof are a part; an A/D converter for converting the analog input signals to corresponding digital signals at a conversion sampling rate; a memory for storing the digital signals from the A/D converter; means for clocking the digital signals into the register at one rate; means for clocking stored digital signals out of the memory at another rate different from said one rate; means for synchronizing both the one rate and the other rate with the conversion sampling rate of the A/D converter; means for varying the sampling rate of the A/D converter; and means for reducing the one rate relative to the other rate by reducing the one rate relative to the conversion sampling rate whereby the proportion of digital signals developed by the A/D converter which are clocked into the memory is reduced as the ratio of the one rate to the other rate is reduced.