Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
241 words
A circuit for producing an output pulse of predetermined amplitude and a width equal to the mid amplitude width of an input pulse from an input pulse source, said circuit comprising: delay line means having an input terminal connected to said input pulse source, a first output terminal and a second output terminal, the output of said delay line at said first output terminal being delayed in time with respect to said input pulse by a first predetermined period and the output of said delay line at said second output terminal being delayed in time with respect to said input pulse by twice said predetermined period; amplifier means connected to said delay line first output terminal for doubling the amplitude of the output of said first terminal; first comparator means having a first input connected to said input pulse source, a second input connected to said amplifier and an output; second comparator means having a first input connected to said amplifier, a second input connected to said delay line second output terminal and an output; gate means having a first input connected to said first comparator output and a second input connected to said second comparator output; a capacitor connected to said amplifier; a voltage divider subcircuit shunted across said capacitor; and, a third comparator having a first input connected to said amplifier, a second input connected to said subcircuit, and an output forming an additional input to said gate means.
Claim 2
Dependent Claim
241 words
A circuit for producing an output pulse of predetermined amplitude and a width equal to the mid amplitude width of an input pulse from an input pulse source, said circuit comprising: delay line means having an input terminal connected to said input pulse source, a first output terminal and a second output terminal, the output of said delay line at said first output terminal being delayed in time with respect to said input pulse by a first predetermined period and the output of said delay line at said second output terminal being delayed in time with respect to said input pulse by twice said predetermined period; amplifier means connected to said delay line first output terminal for doubling the amplitude of the output of said first terminal; first comparator means having a first input connected to said input pulse source, a second input connected to said amplifier and an output; second comparator means having a first input connected to said amplifier, a second input connected to said delay line second output terminal and an output; gate means having a first input connected to said first comparator output and a second input connected to said second comparator output; a capacitor connected to said amplifier; a voltage divider subcircuit shunted across said capacitor; and, a third comparator having a first input connected to said amplifier, a second input connected to said subcircuit, and an output forming an additional input to said gate means.
Claim 3
Dependent Claim
268 words
In an electro-optical label reading system including a label containing coded data, apparatus for optically scanning said label, and a sensor operative in response to light reflected from said label to produce input signal pulses representative of said coded data, the improvement of a pulse width detector circuit comprising: a delay line having an input terminal, a first output terminal and a second output terminal, the delay at said second output terminal being twice that at said first output terminal; means for applying said input signal pulses to said delay line input terminal; amplifier means connected to said delay line first output terminal and operative to produce output pulses equal to twice the output of said input pulses; first and second comparators each having a first and second input terminal and an output terminal; means connecting the output of said amplifier to the second input terminal of both said first and second comparators; means connecting said first comparator first terminal to said input signal pulse applying means; means connecting the second output terminal of said delay line to said second comparator first input terminal; gate means responsive to output signals from both said first and second comparators, said gate means having a first input connected to the output of said first comparator and a second input connected to the output of said second comparator; a capacitor connected to said amplifier; a voltage divider subcircuit shunted across said capacitor; and, a third comparator having a first input connected to said amplifier, a second input connected to said subcircuit, and an output forming an additional input to said gate means.
Claim 4
Dependent Claim
268 words
In an electro-optical label reading system including a label containing coded data, apparatus for optically scanning said label, and a sensor operative in response to light reflected from said label to produce input signal pulses representative of said coded data, the improvement of a pulse width detector circuit comprising: a delay line having an input terminal, a first output terminal and a second output terminal, the delay at said second output terminal being twice that at said first output terminal; means for applying said input signal pulses to said delay line input terminal; amplifier means connected to said delay line first output terminal and operative to produce output pulses equal to twice the output of said input pulses; first and second comparators each having a first and second input terminal and an output terminal; means connecting the output of said amplifier to the second input terminal of both said first and second comparators; means connecting said first comparator first terminal to said input signal pulse applying means; means connecting the second output terminal of said delay line to said second comparator first input terminal; gate means responsive to output signals from both said first and second comparators, said gate means having a first input connected to the output of said first comparator and a second input connected to the output of said second comparator; a capacitor connected to said amplifier; a voltage divider subcircuit shunted across said capacitor; and, a third comparator having a first input connected to said amplifier, a second input connected to said subcircuit, and an output forming an additional input to said gate means.