US4045618A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Device for synchronizing a binary data train in relation to a reference train
Assignee: Alcatel CIT SA
•
Filing: 1976-01-29
•
Granted: 1977-08-30
•
Expires: 1996-01-29
Abstract
Abstract The invention comes within the field of digital transmission and concerns e synchronization of two bit trains in relation to the beginning of a frame. According to the invention, one of the trains crosses a memory of the FIFO type, whose writing speed corresponds to the frequency of that train and whose reading is controlled by a detector of the locking word in that frame and by a signal indicating the synchronization of the two trains. Application: digital PCM terminals comprising thirty telephone channels.
Inventors
- 👤 Jean-Louis Lagarde
- 👤 Gilles Gauriat
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 15:51
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/05; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/062; H04J3/0626
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
163 words
A device for synchronizing a binary data series train in relation to a reference train, the two trains having identical frequencies and being subdivided by predetermined locking bits into frames of identical lengths, the device comprising: a series/parallel-type first converter receiving the binary train in series and delivering this train, cut up randomly in words of q bits (q = 2, 3, . . . ); a FIFO-type memory having q bits per memory cell therein and receiving words at a regular writing speed of l/q of the frequency; a parallel/series-type second converter receiving the output of said memory; a decoder for detecting the predetermined locking bits from an output train of said second converter; logic control means for receiving a pulse clock signal and frame synchronization signal of the reference train as well as the output of said decoder, for controlling the reading operation of said memory; and gate means for delivering the binary train to a synchronized output of the device.
Claim 2
Independent Claim
163 words
A device for synchronizing a binary data series train in relation to a reference train, the two trains having identical frequencies and being subdivided by predetermined locking bits into frames of identical lengths, the device comprising: a series/parallel-type first converter receiving the binary train in series and delivering this train, cut up randomly in words of q bits (q = 2, 3, . . . ); a FIFO-type memory having q bits per memory cell therein and receiving words at a regular writing speed of l/q of the frequency; a parallel/series-type second converter receiving the output of said memory; a decoder for detecting the predetermined locking bits from an output train of said second converter; logic control means for receiving a pulse clock signal and frame synchronization signal of the reference train as well as the output of said decoder, for controlling the reading operation of said memory; and gate means for delivering the binary train to a synchronized output of the device.
Claim 3
Dependent Claim
47 words
The device as defined in claim 1, further comprising a shift register between said second converter and said decoder, which shift register receives an output series train of said second converter, and the capacity of which shift register corresponds to the number of the predetermined locking bits.
References Cited (Backward Citations)
US3575557A
Cited
US3867579A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-08-29 | 1981-02-28 | 1981-08-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-08-29 | 1985-02-28 | 1985-08-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-08-29 | 1989-02-28 | 1989-08-30 | $7700.00 | Window Closed / Lapsed |