US4045793A
Expired / Lapsed
US
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Digital to analog converter
Assignee: Motorola Solutions Inc
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Filing: 1975-09-29
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Granted: 1977-08-30
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Expires: 1995-09-29
Abstract
Abstract An MOS digital to analog converter on a semiconductor chip includes N digital inputs and a single analog output. The digital inputs control circuitry which switches in various combinations of 2 0 +2 1 +...2 N-1 IGFETs with substantially similar voltage current characteristics coupled between a voltage supply conductor and an analog current output conductor. The IGFETs are arranged in N groups, each group being controlled, respectively, by one of the digital inputs. The number of IGFETs in each group is given by the expression 2 n-1 where 1≦n≦N. A control circuit including a plurality of substantially identical diode-connected IGFETs is coupled between a constant current source and the voltage supply conductor. The voltage supply conductor provides a voltage which is gated by means of switching circuitry controlled by the digital inputs to the gate electrodes, respectively, of each of the groups of IGFETs. This circuit controls the ratio between the analog output current and the current of the current source, and also assures that each of the IGFETs connected to the analog output conductor operates in the saturation portion of its current-voltage characteristic.
Inventors
- 👤 Jerry Dale Moench
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 23:46
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/06; H03M1/08; H03M1/0863
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
274 words
A digital to analog converter comprising: N binary inputs for applying N signals representative of an N-bit binary number to said digital to analog converter, N being an integer; a first conductor for conducting an analog current representative of an N-bit binary number; N groups of field effect transistors, each of said field effect transistors having its source electrode connected to a reference voltage conductor and having its drain electrode connected to said first conductor, the gate electrodes of all field effect transistors in each of said groups, respectively, being connected to the gate electrodes of all other field effect transistors in the same group, but not to the gate electrodes of the field effect transistors of any of the other of said groups, each of said groups, respectively, including 2 n of said field effect transistors, wherein n has a separate integer value in the range 0 ≦ n ≦ (N-1) for each of said groups, respectively; input means coupled to said N inputs and to said gate conductors of each of said groups of field effect transistors for switching the field effect transistors in each of said groups, respectively, into an ON condition in response to said N signals; reference means coupled to said input means for generating a reference voltage which varies in substantially the same manner as the threshold voltages of said field effect transistors; wherein said input means further includes means for switchably coupling said reference voltage to said gate electrodes of each of said N groups, respectively in response to said N signals in order to switch ON selected ones of said N groups of field effect transistors.
Claim 2
Dependent Claim
274 words
A digital to analog converter comprising: N binary inputs for applying N signals representative of an N-bit binary number to said digital to analog converter, N being an integer; a first conductor for conducting an analog current representative of an N-bit binary number; N groups of field effect transistors, each of said field effect transistors having its source electrode connected to a reference voltage conductor and having its drain electrode connected to said first conductor, the gate electrodes of all field effect transistors in each of said groups, respectively, being connected to the gate electrodes of all other field effect transistors in the same group, but not to the gate electrodes of the field effect transistors of any of the other of said groups, each of said groups, respectively, including 2 n of said field effect transistors, wherein n has a separate integer value in the range 0 ≦ n ≦ (N-1) for each of said groups, respectively; input means coupled to said N inputs and to said gate conductors of each of said groups of field effect transistors for switching the field effect transistors in each of said groups, respectively, into an ON condition in response to said N signals; reference means coupled to said input means for generating a reference voltage which varies in substantially the same manner as the threshold voltages of said field effect transistors; wherein said input means further includes means for switchably coupling said reference voltage to said gate electrodes of each of said N groups, respectively in response to said N signals in order to switch ON selected ones of said N groups of field effect transistors.
Claim 3
Dependent Claim
52 words
The digital to analog converter as recited in claim 1 wherein said reference means includes a second conductor, and at least one field effect transistor having its source coupled to said reference voltage conductor and its gate electrode coupled to said voltage conductor, and a current source coupled to said second conductor.
Claim 4
Dependent Claim
97 words
The digital to analog converter as recited in claim 1 wherein said means for switchably coupling said reference voltage includes N field effect transistors coupled, respectively, between said second conductor and said gate electrodes of each of said N groups of field effect transistors, and additionally includes N field effect transistors coupled, respectively, between said reference voltage conductor and said gate electrodes of each of said N groups for electrically coupling said gate electrodes of each of said N groups, respectively, to said second conductor or to said reference voltage conductor in response to said N signals.
Claim 5
Dependent Claim
228 words
A digital to analog converter comprising: N binary inputs for applying N signals representative of an N bit binary number to said digital to analog converter, N being an integer; a first conductor for conducting an analog current representative of said N bit binary number; N groups of FET electron control devices, each having a control electrode and two controlled electrodes thereof, each of said electron control devices being connected by means of its controlled electrodes to a reference voltage conductor and to said first conductor, the control electrodes of all electron control devices in each of said groups, respectively, being connected to the control electrodes of the other electron control devices in the same one of said groups, each of said groups, respectively, including 2 n of said electron control devices, wherein n has a separate integer value in the range 0 ≦ n ≦ (N-1) for each one of said groups, respectively; reference means for generating a reference voltage which varies substantially at the same rate as the threshold voltage of said electron control devices; and input means coupled to said N inputs and to said control electrodes of each of said groups of electron control devices and to said reference means for coupling said reference voltage to said control electrodes of each of said groups of electron control devices in response to said N signals.
Claim 6
Dependent Claim
228 words
A digital to analog converter comprising: N binary inputs for applying N signals representative of an N bit binary number to said digital to analog converter, N being an integer; a first conductor for conducting an analog current representative of said N bit binary number; N groups of FET electron control devices, each having a control electrode and two controlled electrodes thereof, each of said electron control devices being connected by means of its controlled electrodes to a reference voltage conductor and to said first conductor, the control electrodes of all electron control devices in each of said groups, respectively, being connected to the control electrodes of the other electron control devices in the same one of said groups, each of said groups, respectively, including 2 n of said electron control devices, wherein n has a separate integer value in the range 0 ≦ n ≦ (N-1) for each one of said groups, respectively; reference means for generating a reference voltage which varies substantially at the same rate as the threshold voltage of said electron control devices; and input means coupled to said N inputs and to said control electrodes of each of said groups of electron control devices and to said reference means for coupling said reference voltage to said control electrodes of each of said groups of electron control devices in response to said N signals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-08-29 | 1981-02-28 | 1981-08-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-08-29 | 1985-02-28 | 1985-08-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-08-29 | 1989-02-28 | 1989-08-30 | $7700.00 | Window Closed / Lapsed |