US4054755A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Conference circuit for pulse coded modulated telephony
Assignee: AG Communication Systems Corp
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Filing: 1976-10-14
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Granted: 1977-10-18
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Expires: 1996-10-14
Abstract
Abstract A method of providing a multi-port conference circuit for use in a telephone switching system employing pulse coded modulated signals for transmission and supervision. Samplings of coded information are employed as a source of conference data and comparison with the digital information contained therein is employed to choose the speaker in a conference group. Included circuitry provides compensation for degradation caused by speech clipping and noise.
Inventors
- 👤 David Quon Lee
- 👤 Donald W. McLaughlin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 01:58
CPC Classifications
H; H04; H04M; H04M3/00; H04M3/42; H04M3/56; H04M3/568; H04M3/569
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
405 words
In a pulse code modulated communication system, a plurality of communication channels arranged on a multiplexed basis, a switching system including a memory access by said communication channels and a conference circuit including, a first register connected to said memory operated to store the coded value of information from each of said channels conducted sequentially through said memory, a second register connected to said first register and including an output circuit connection to said channels, a first comparator circuit connected to said first and to said second registers operated to compare the coded value of information stored in said first and said second registers and in response to determination that the value of information stored in said first register is less than the value of information stored in said second register to cause the coded value of information stored in said first register to be transferred to said second register for transfer of said coded value of information to said channels under control of said switching system, counting means connected to said memory periodically incremented in response to signals from said memory, a fourth register connected to said counting means operated to store the count of said counting means, a fifth register connected to said fourth register, said count stored in said fourth register transferred to said fifth register in response to signals from said switching system, and a second comparator circuit connected to said fourth and fifth registers and including a circuit connection to said channels, operated in response to determination that the count stored in said fourth and fifth registers are equal, to inhibit transfer information to said channels, the improvement comprising: a third comparator circuit connected to said fourth and fifth registers operated in response to determination that the count stored in said fourth and fifth registers are equal; a sixth register connected to said second register and to said switching system operated in response to a signal of at least a predetermined digital value stored in said second register; and gating means connected to said second comparator circuit, to said third comparator circuit, to said sixth register, and to said switching system, and including a plurality of output circuit connections to said first comparator circuit, selectively operated in response to said second and third comparator circuits and said sixth register to operate said first comparator circuit to modify the coded values of information stored in said first and said second registers.
Claim 2
Dependent Claim
405 words
In a pulse code modulated communication system, a plurality of communication channels arranged on a multiplexed basis, a switching system including a memory access by said communication channels and a conference circuit including, a first register connected to said memory operated to store the coded value of information from each of said channels conducted sequentially through said memory, a second register connected to said first register and including an output circuit connection to said channels, a first comparator circuit connected to said first and to said second registers operated to compare the coded value of information stored in said first and said second registers and in response to determination that the value of information stored in said first register is less than the value of information stored in said second register to cause the coded value of information stored in said first register to be transferred to said second register for transfer of said coded value of information to said channels under control of said switching system, counting means connected to said memory periodically incremented in response to signals from said memory, a fourth register connected to said counting means operated to store the count of said counting means, a fifth register connected to said fourth register, said count stored in said fourth register transferred to said fifth register in response to signals from said switching system, and a second comparator circuit connected to said fourth and fifth registers and including a circuit connection to said channels, operated in response to determination that the count stored in said fourth and fifth registers are equal, to inhibit transfer information to said channels, the improvement comprising: a third comparator circuit connected to said fourth and fifth registers operated in response to determination that the count stored in said fourth and fifth registers are equal; a sixth register connected to said second register and to said switching system operated in response to a signal of at least a predetermined digital value stored in said second register; and gating means connected to said second comparator circuit, to said third comparator circuit, to said sixth register, and to said switching system, and including a plurality of output circuit connections to said first comparator circuit, selectively operated in response to said second and third comparator circuits and said sixth register to operate said first comparator circuit to modify the coded values of information stored in said first and said second registers.
Claim 3
Dependent Claim
75 words
In a pulse code modulated communication system as claimed in claim 1, wherein: said gating means comprise a plurality of gate circuits including a first gate circuit connected to said second comparator circuit and to said switching system, and including an output circuit connection to said first comparator circuit, operated in response to said second comparator circuit, to operate said first comparator circuit to modify the coded value of information stored in said first register.
Claim 4
Dependent Claim
75 words
In a pulse code modulated communication system as claimed in claim 1, wherein: said gating means comprise a plurality of gate circuits including a second gate circuit connected to said third comparator circuit, and to said switching system, and including an output circuit connection to said first comparator circuit, operated in response to said third comparator circuit, to operate said first comparator circuit to modify the coded value of information stored in said second register.
Claim 5
Dependent Claim
77 words
In a pulse code modulated communication system as claimed in claim 2, wherein: said gating means comprise a plurality of gates including a third gate connected to said sixth register and to said first gate circuit and including an output circuit connection to said first comparator circuit, operated in response to said sixth register and said first gate circuit, to operate said first comparator circuit to modify the coded value of information stored in said first register.
Claim 6
Dependent Claim
79 words
In a pulse code modulated communication system as claimed in claim 3, wherein: said gating means comprise a plurality of gate circuits including a fourth gate circuit connected to said sixth register and to said second gate circuit and including an output circuit connection to said first comparator circuit, operated in response to said sixth register and said second gate circuit, to operate said first comparator circuit to modify the coded value of information stored in said second register.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-10-17 | 1981-04-18 | 1981-10-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-10-17 | 1985-04-18 | 1985-10-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-10-17 | 1989-04-18 | 1989-10-18 | $7700.00 | Window Closed / Lapsed |