Microcomputer processing approach for a non-volatile TV station memory tuning system

Claim 2

A broadcast receiver tuning system for tuning said broadcast receiver to a selected frequency comprising: first means for storing digital tune words responsive to a binary address for outputting a selected said digital tune word, second means for storing said selected digital tune word and said binary address operably associated with said first means for storing, a microcomputer operable for selectively changing said digital tune words in said first and second means for storing, and means for converting said digital tune word stored in said second means for storing into an analog voltage operative to tune said broadcast receiver to said selected frequency.

Claim 3

A tuning system of claim 1 wherein said microcomputer comprises: means for incrementing and decrementing said digital tune word stored in said second means in updating said digital tune word, means for providing a plurality of operating instructions and logic functions operative of said microcomputer, means for storing binary data responsive to said binary address and said instructions operative for incrementing and decrementing said digital tune word stored in said second means for storing, and means for inputting control functions operably associated with said means for providing a plurality of operating instructions.

Claim 4

A tuning system of claim 1 wherein said means for converting comprises: a pulse width modulator generator for outputting a digital signal proportional to said digital tune word, and a digital to analog converter for converting said digital signal into said analog voltage for tuning said broadcast receiver to said selected frequency.

Claim 5

A tuning system of claim 1 wherein said broadcast receiver comprises a television set.

Claim 6

A tuning system of claim 1 wherein said first means for storing digital tune words comprises a nonvolatile random access memory.

Claim 7

A tuning system of claim 1 wherein said second means for storing said digital tune word and said binary address comprises a shift register.

Claim 8

A tuning system of claim 2 wherein said means for incrementing and decrementing comprises an arithmetic logic unit.

Claim 9

A tuning system of claim 7 wherein said arithmetic logic unit comprises: a plurality of shift registers, a one bit full adder operably associated with said plurality of shift registers for adding and subtracting said digital tune words and said binary data stored in said plurality of shift registers, and means for storing said digital tune words and said binary data operably associated with said plurality of shift registers and said one bit full adder.

Claim 10

A tuning system of claim 2 wherein said means for providing a plurality of operating instructions and logic functions comprises: a program counter, an instruction memory responsive to said program counter for outputting binary instructions, and a program logic array responsive to said binary instructions for outputting a plurality of said logic functions.

Claim 11

A tuning system of claim 9 further including a microprogram counter operably associated with said program counter.

Claim 12

A broadcast receiver tuning system for tuning said broadcast receiver to a selected frequency comprising: a first memory matrix for storing digital tune words corresponding to said selected frequency, means for generating a binary address for addressing said digital tune word from said first memory, means for storing said binary address and said addressed digital tune words operably associated with said first memory and said means for generating said binary address, means connected to said address and tune word storing means for incrementing and decrementing said addressed digital tune word for updating said digital tune word, means responsive to said binary address for outputting selected binary data from a second memory matrix, said binary data used for incrementing and decrementing said addressed digital tune word, means connected to said incrementing and decrementing means for providing a plurality of operating instructions and logic functions operative for updating said digital tune word, means for inputting control functions operably associated with said means for providing a plurality of operating instructions, and means for converting said addressed digital tune word into an analog voltage operative to tune said broadcast receiver to said selected frequency.

Claim 13

A broadcast receiver tuning system for tuning said broadcast receiver to a selected frequency comprising: a first memory matrix for storing digital tune words corresponding to said selected frequency, means for generating a binary address for addressing said digital tune word from said first memory, means for storing said binary address and said addressed digital tune words operably associated with said first memory and said means for generating said binary address, means connected to said address and tune word storing means for incrementing and decrementing said addressed digital tune word for updating said digital tune word, means responsive to said binary address for outputting selected binary data from a second memory matrix, said binary data used for incrementing and decrementing said addressed digital tune word, means connected to said incrementing and decrementing means for providing a plurality of operating instructions and logic functions operative for updating said digital tune word, means for inputting control functions operably associated with said means for providing a plurality of operating instructions, and means for converting said addressed digital tune word into an analog voltage operative to tune said broadcast receiver to said selected frequency.

Claim 14

A tuning system of claim 11 wherein said digital tune words further correspond to a plurality of VHF and UHF television channels.

Claim 15

A tuning system of claim 11 wherein said means for storing said binary address and said addressed digital tune word comprises a shift register.

Claim 16

A tuning system of claim 11 wherein said means for incrementing and decrementing comprises: a plurality of shift registers, a one bit full adder operably associated with said plurality of shift registers for adding and subtracting said digital tune words and said binary data stored in said plurality of shift registers, and means for storing said digital tune words and said binary data operably associated with said plurality of shift registers and said one bit full adder.

Claim 17

A tuning system of claim 11 wherein said means for providing a plurality of operating instructions and logic functions comprises: a program counter, an instruction memory responsive to said program counter for outputting binary instructions, and a program logic array responsive to said binary instructions for outputting a plurality of said logic functions.

Claim 18

A tuning system of claim 11 wherein said means for inputting logic control functions comprises an input logic status switch.

Claim 19

A tuning system of claim 11 wherein said means for converting comprises: a pulse width modulator generator for outputting a digital signal proportional to said digital tune word, and a digital to analog converter for converting said digital signal into said analog voltage for tuning said broadcast receiver to said selected frequency.

Claim 20

A tuning system of claim 15 further including a microprogram counter operably associated with said program counter.

Claim 21

A tuning system of claim 14 further including an automatic channel shift encode for normalization of a binary VHF increment value comprising one of said binary data stored in said second memory matrix.

Claim 22

A television tuning system for tuning said television to a selected VHF and UHF channel comprising: a first memory matrix for storing digital tune words corresponding to said VHF and UHF channels, means for generating a binary address on a multibus line for outputting said digital tune words from said first memory, a shift register operably associated with said first memory and said means for generating a binary address for storing said digital tune word and said binary address, an arithmetic logic unit for incrementing and decrementing said digital tune word stored in said serial shift register in updating said digital tune word, means for providing a plurality of operating instructions and logic functions operative in updating said digital tune word, a second memory matrix for storing binary data used in incrementing and decrementing said digital tune word, said second memory matrix responsive to said binary address and said operating instructions, said second memory matrix also operably associated with said arithmetic logic unit, an input logic status switch for inputting control functions operably associated with said means for providing a plurality of operating instructions, a pulse width modulator responsive to said digital tune word stored in said shift register for outputting a digital signal proportional to said digital tune word, and means for converting said digital signal to an analog voltage operative to tune said television to said selected UHF or VHF channel.

Claim 23

A television tuning system for tuning said television to a selected VHF and UHF channel comprising: a first memory matrix for storing digital tune words corresponding to said VHF and UHF channels, means for generating a binary address on a multibus line for outputting said digital tune words from said first memory, a shift register operably associated with said first memory and said means for generating a binary address for storing said digital tune word and said binary address, an arithmetic logic unit for incrementing and decrementing said digital tune word stored in said serial shift register in updating said digital tune word, means for providing a plurality of operating instructions and logic functions operative in updating said digital tune word, a second memory matrix for storing binary data used in incrementing and decrementing said digital tune word, said second memory matrix responsive to said binary address and said operating instructions, said second memory matrix also operably associated with said arithmetic logic unit, an input logic status switch for inputting control functions operably associated with said means for providing a plurality of operating instructions, a pulse width modulator responsive to said digital tune word stored in said shift register for outputting a digital signal proportional to said digital tune word, and means for converting said digital signal to an analog voltage operative to tune said television to said selected UHF or VHF channel.

Claim 24

A tuning system of claim 20 further including an automatic channel shift encode for normalization of a binary VHF increment value comprising one of said binary data stored in said second memory matrix.

Claim 25

A tuning system of claim 20 wherein said means for providing a plurality of operating instructions and logic functions comprises: a program counter, an instruction memory responsive to said program counter for outputting binary instructions, and a program logic array responsive to said binary instructions for outputting a plurality of said logic functions.

Claim 26

A tuning system of claim 22 further including a microprogram counter operably associated with said program counter.