US4094079A — Single medium audio-visual teaching machine

Claim 1

Independent Claim 759 words

In an audio-visual teaching machine for use with a source record comprising an audio portion, a video control portion having video display pulses entrained therein, and a source control portion having a control pulse entrained therein in one of a predetermined number of response states, the teaching machine including: a source record playback unit including a playback portion for receiving the source record, providing a composite source output signal having an audio portion corresponding to the audio portion of the source record, a video control portion corresponding to the video control portion of the source record, and a source control portion corresponding to the source control portion of the source record; and a pause control portion for interrupting the operation of the playback portion thereof in response to a pause signal applied thereto; an audio output unit for providing an audible output signal in response to an audio signal applied thereto; and, a video display unit for providing a visual output signal in response to a composite video signal applied thereto; the improvement comprising: a source control unit means connected to the source record playback unit, the source control unit means including a response control portion having a plurality of actuatable response input elements, each response input element providing a response input signal in a predetermined one of the response states in response to the actuation thereof, the source control unit means for receiving the source control portion of the composite source output signal, detecting the control pulse entrained in the source control portion, initiating production of the pause control signal for application to the pause control portion of the source record playback unit in response to detecting a control pulse having one of a selected plurality of the response states, receiving each of the response input signals provided by the response input elements upon actuation thereof, comparing the response state of the detected control pulse and the response state of the received response input signal, and terminating production of the pause signal when the response state of the detected control pulse is equal to the response state of the received response input signal; a video control unit connected to the source record playback unit and to the video display unit, the video control unit comprising: an asyncronous interface circuit means connected to the source record playback unit, the asynchronous interface circuit means for receiving the video control portion of the composite source output signal, detecting the video display pulses entrained in the video control portion, providing an input data signal having input data pulses entrained therein corresponding to the detected video display pulses, and providing an input clock signal having an input clock pulse entrained therein in response to detecting a predetermined number of the video display pulses; a timer circuit means for providing an output clock signal having output clock pulses entrained therein at a predetermined output clock rate, providing an end-of-scan-line signal having end-of-scan-line pulses entrained therein at a predetermined end-of-scan-line rate, and providing an end-of-field signal having end-of-field pulses entrained therein at a predetermined end-of-field rate; a memory control circuit means connected to the asynchronous interface circuit means and to the timer circuit means, the memory control circuit means for receiving the input data signal, the input clock signal and the output clock signal, storing each input data pulse entrained in the received input data signal at a predetermined storage location in response to receiving each input clock pulse entrained in the input clock signal, and providing a video output signal having a video data pulse entrained therein corresponding to the input data pulse stored at a predetermined storage location in response to each output clock pulse entrained in the output clock signal; a video processing circuit means connected to the memory control circuit means, to the timer circuit means, and to the video display unit, the video processing circuit means for receiving the video output signals, the end-of-scan-line signal, and the end-of-field signal, producing a horizontal sync pulse in response to receiving each end-of-scan-line pulse entrained in the end-of-scan-line signal, producing a vertical synch pulse in response to receiving each end-of-field pulse entrained in the end-of-field signal, and adding the horizontal and vertical sync pulses to the received video output signal for application to the video display unit as the composite video signal; and, means connected to the source record playback unit and to the audio output unit for receiving the audio portion of the composite source output signal and applying the received audio portion to the audio output unit as the audio signal.

Claim 2

Dependent Claim 759 words

In an audio-visual teaching machine for use with a source record comprising an audio portion, a video control portion having video display pulses entrained therein, and a source control portion having a control pulse entrained therein in one of a predetermined number of response states, the teaching machine including: a source record playback unit including a playback portion for receiving the source record, providing a composite source output signal having an audio portion corresponding to the audio portion of the source record, a video control portion corresponding to the video control portion of the source record, and a source control portion corresponding to the source control portion of the source record; and a pause control portion for interrupting the operation of the playback portion thereof in response to a pause signal applied thereto; an audio output unit for providing an audible output signal in response to an audio signal applied thereto; and, a video display unit for providing a visual output signal in response to a composite video signal applied thereto; the improvement comprising: a source control unit means connected to the source record playback unit, the source control unit means including a response control portion having a plurality of actuatable response input elements, each response input element providing a response input signal in a predetermined one of the response states in response to the actuation thereof, the source control unit means for receiving the source control portion of the composite source output signal, detecting the control pulse entrained in the source control portion, initiating production of the pause control signal for application to the pause control portion of the source record playback unit in response to detecting a control pulse having one of a selected plurality of the response states, receiving each of the response input signals provided by the response input elements upon actuation thereof, comparing the response state of the detected control pulse and the response state of the received response input signal, and terminating production of the pause signal when the response state of the detected control pulse is equal to the response state of the received response input signal; a video control unit connected to the source record playback unit and to the video display unit, the video control unit comprising: an asyncronous interface circuit means connected to the source record playback unit, the asynchronous interface circuit means for receiving the video control portion of the composite source output signal, detecting the video display pulses entrained in the video control portion, providing an input data signal having input data pulses entrained therein corresponding to the detected video display pulses, and providing an input clock signal having an input clock pulse entrained therein in response to detecting a predetermined number of the video display pulses; a timer circuit means for providing an output clock signal having output clock pulses entrained therein at a predetermined output clock rate, providing an end-of-scan-line signal having end-of-scan-line pulses entrained therein at a predetermined end-of-scan-line rate, and providing an end-of-field signal having end-of-field pulses entrained therein at a predetermined end-of-field rate; a memory control circuit means connected to the asynchronous interface circuit means and to the timer circuit means, the memory control circuit means for receiving the input data signal, the input clock signal and the output clock signal, storing each input data pulse entrained in the received input data signal at a predetermined storage location in response to receiving each input clock pulse entrained in the input clock signal, and providing a video output signal having a video data pulse entrained therein corresponding to the input data pulse stored at a predetermined storage location in response to each output clock pulse entrained in the output clock signal; a video processing circuit means connected to the memory control circuit means, to the timer circuit means, and to the video display unit, the video processing circuit means for receiving the video output signals, the end-of-scan-line signal, and the end-of-field signal, producing a horizontal sync pulse in response to receiving each end-of-scan-line pulse entrained in the end-of-scan-line signal, producing a vertical synch pulse in response to receiving each end-of-field pulse entrained in the end-of-field signal, and adding the horizontal and vertical sync pulses to the received video output signal for application to the video display unit as the composite video signal; and, means connected to the source record playback unit and to the audio output unit for receiving the audio portion of the composite source output signal and applying the received audio portion to the audio output unit as the audio signal.

Claim 3

Dependent Claim 404 words

The audio-visual teaching machine of claim 1 wherein the memory control circuit means of the video control unit is further defined to include: an input address counter circuit means connected to the asynchronous interface circuit means, the input address counter circuit means for receiving the input clock signal, incrementing an input address count in response to receiving each input clock pulse entrained in the input clock signal, providing an input address signal corresponding to the input address count, and resetting the input address count to an initial input address value in response to receiving a predetermined number of the input clock pulses; an output address counter circuit means connected to the timer circuit means, the output address counter circuit means for receiving the output clock signal, incrementing an output address count in response to receiving each output clock pulse entrained in the output clock signal, providing an output address signal corresponding to the output address count, and periodically resetting the output address count to an initial output address value in response to receiving a predetermined number of the output clock pulses; an input/output control circuit means connected to the input address counter circuit means and to the output address counter circuit means, the input/output control circuit means for receiving the input address signal and the output address signal, comparing the received input address signal and the received output address signal, providing an I/O control signal in an input state when the received input address signal is equal to the received output address signal, and providing the I/O control signal in an output state when the received input address is not equal to the received output address signal; and, a memory circuit means connected to the asynchronous interface circuit means, to the output address counter circuit means and to the input/output control circuit means, the memory circuit means for receiving the input data signal, the output address signal and the I/O control signal, storing each input data pulse entrained in the received input data signal at a predetermined storage location corresponding to the received output address signal in response to simultaneously receiving the I/O control signal in the input state, and providing a video output signal having a video data pulse entrained therein corresponding to the input data pulse stored at the predetermined storage location corresponding to the received output address signal in response to simultaneously receiving the I/O control signal in the output state.

Claim 4

Dependent Claim 112 words

The audio-visual teaching machine of claim 2 wherein the source control unit means is further characterized as providing a frame control signal having a frame control pulse entrained therein when the response state of the received response input signal is equal to the response state of the detected control pulse, and wherein the input address counter circuit means of the video control unit is further characterized as being connected to the source control unit means, the input address counter circuit means receiving the frame control signal and resetting the input address count to the initial input address value in response to receiving the frame control pulse entrained in the frame control signal.

Claim 5

Dependent Claim 62 words

The audio-visual teaching machine of claim 3 wherein one of the response states is further characterized as a frame erase state, and wherein the source control unit means is further characterized as providing the frame control signal having the frame control pulse entrained therein in response to detecting a control pulse in the frame erase state entrained in the source control portion.

Claim 6

Dependent Claim 172 words

The audio-visual teaching machine of claim 4 wherein the video control unit is further defined to include: a frame erase circuit means interposed between the source control unit and the input address counter circuit of the video control unit and connected to the memory circuit, the frame erase circuit means for receiving the frame control signal provided by the source control unit means, producing a clear signal having a clear pulse entrained therein for application to the input address counter circuit means in place of the frame control signal, producing an I/O control signal in the input state for application to the memory circuit means in place of the I/O control signal produced by the input/output control circuit means, and producing a blank data signal having a predetermined number of blank data pulses entrained therein corresponding to a predetermined type of input data pulse provided by the asyncronous interface circuit means for application to the memory circuit means in place of the input data signal provided by the asyncronous interface circuit means.

Claim 7

Dependent Claim 444 words

The audio-visual teaching machine of claim 2 wherein each of the predetermined number of input data pulses provided by the asynchronous interface circuit means comprises an input character code; wherein the output address counter circuit means is further characterized as incrementing a scan-line count in response to incrementing the output address count a predetermined number of times, for providing a scan-line signal corresponding to the scan-line count, and for periodically resetting the scan-line count to a predetermined scan-line starting value in response to incrementing the scan-line count a predetermined number of times; wherein the timer circuit means is further characterized as providing a bit clock signal having bit clock pulses entrained therein at a predetermined bit clock rate; and wherein the memory circuit means is further defined to include: a character memory circuit means connected to the asynchronous interface circuit means, to the output address counter circuit means and to the input/output control circuit means, the character memory circuit means for receiving the input data signal, the output address signal and the I/O control signal, storing each input character code consisting of the predetermined number of input data pulses entrained in the received input data signal at a predetermined storage location corresponding to the received output address signal in response to simultaneously receiving the I/O control signal in the input state, and providing an output character signal having an output character code entrained therein corresponding to the input character code stored at the predetermined storage location corresponding to the received output address signal in response to simultaneously receiving the I/O control signal in the output state; a character generator means connected to the character memory means and to the output address control circuit means, the character generator means for receiving the output character signal and the scan-line signal, generating a character bit pattern corresponding to the output character code entrained in the received output character signal, each character bit pattern being comprised of a predetermined number of scan-line bit patterns, and providing a bit pattern signal having bit pattern pulses entrained therein corresponding to the scan-line bit pattern of the generated character bit pattern corresponding to the received scan-line signal; and, a video shift register means connected to the character generator means, to the timer circuit means, and to the video processing circuit means, the video shift register means for receiving the bit pattern signal and the bit clock signal, and providing a consecutive one of the bit pattern pulses entrained in the received bit pattern signal for application to the video processing circuit means as the video output signal in response to each bit clock pulse entrained in the received bit clock signal.

Claim 8

Dependent Claim 34 words

The audio-visual teaching machine of claim 1 wherein the means for receiving the audio portion of the composite source output signal are further characterized as comprising a portion of the source control unit means.

Claim 9

Dependent Claim 124 words

The audio-visual teaching machine of claim 1 wherein the audio output unit and the video display unit are further characterized as comprising portions of a television receiver including an RF receiver portion, the audio-visual teaching machine further comprising: an RF interface circuit means interposed between the video control unit means and the video display unit portion of the television receiver, and interposed between the source control unit means and the audio output unit portion of the televison receiver, the RF interface circuit means for receiving the composite video signal and the audio signal, and modulating the received composite video signal and the received audio signal onto an RF carrier having a predetermined frequency for application to the RF receiver portion of the television receiver.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1981-06-12	1981-12-12	1982-06-13	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1985-06-12	1985-12-12	1986-06-13	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1989-06-12	1989-12-12	1990-06-13	$7700.00	Window Closed / Lapsed

Single medium audio-visual teaching machine

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