US4099028A
Expired / Lapsed
US
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Asynchronous multiplexer-demultiplexer
Assignee: Raytheon Co
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Filing: 1977-04-21
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Granted: 1978-07-04
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Expires: 1997-04-21
Abstract
Abstract An asynchronous multiplexer-demultiplexer for pulse-coded data transmission over a single communication link, such as a laser beam link, at a predetermined transmitter pulse clock rate sufficiently high to accommodate a plurality of source ports and corresponding destination ports wherein each source port includes a plurality of buffer memories for accumulation of data blocks to be transmitted, means for encoding the data source clock rate into a 20-bit word, and means for generating an interrupt signal to the transmitter. A priority interrupt system controls the transmitter to transmit blocks of data from the source ports on a predetermined order of priority giving sources of higher data rate higher priority. Each block of data transmitted is preceded by a header which includes a preamble and block sync codes, a source clock code, a source port identification (ID) code, and a source word length code. The receiver decodes the ID code from the header to enable the source clock code and the word length code for a block of data to be routed to a destination port where that block of data, itself, is stored in the next one of a plurality of buffer memories, and the source clock code is decoded to produce an output clock rate for reading out data from the buffer memories of the destination port on a first in, first out basis. The word length code is employed by the destination port if necessary, for converting data from serial to parallel form.
Inventors
- 👤 Jacob T. Towson, IV
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 18:47
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/24
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
184 words
An asynchronous multiplexer for pulse-coded data transmission over a single communication link from a transmitter having a priority interrupt system for servicing a plurality of source ports, one source port for each of a plurality of data sources operating independently of each other, each at a data clock rate F n sufficiently low as compared to a clock rate F TX of transmission by said transmitter that their sum does not exceed EF TX , where E is an efficiency factor, each source port including at least three input buffer memories to be used in rotation for accumulating successive blocks of data bits to be transmitted, means for generating a priority interrupt signal transmitted to said priority interrupt system of said transmitter each time an input buffer memory is filled with a block of data to be transmitted, and means responsive to said interrupt system of said transmitter for selecting said input buffer memories as filled in rotation for transmission over said link at said clock rate F TX , one input buffer memory selected for each priority interrupt response to an interrupt signal.
Claim 2
Dependent Claim
184 words
An asynchronous multiplexer for pulse-coded data transmission over a single communication link from a transmitter having a priority interrupt system for servicing a plurality of source ports, one source port for each of a plurality of data sources operating independently of each other, each at a data clock rate F n sufficiently low as compared to a clock rate F TX of transmission by said transmitter that their sum does not exceed EF TX , where E is an efficiency factor, each source port including at least three input buffer memories to be used in rotation for accumulating successive blocks of data bits to be transmitted, means for generating a priority interrupt signal transmitted to said priority interrupt system of said transmitter each time an input buffer memory is filled with a block of data to be transmitted, and means responsive to said interrupt system of said transmitter for selecting said input buffer memories as filled in rotation for transmission over said link at said clock rate F TX , one input buffer memory selected for each priority interrupt response to an interrupt signal.
Claim 3
Dependent Claim
200 words
An asynchronous multiplexer as defined in claim 1 including means for transmitting a header with each block of data from each source port, said header including a source identification number and a source data clock rate code and including an asynchronous demultiplexer connected to receive transmitted data over said communication link, said demultiplexer comprising a receiver and a plurality of destination ports, one destination port associated with each source port, said receiver comprising means for decoding said identification code and means responsive to said decoding means for routing to the associated destination port the source data clock rate code and data, each destination port comprising a plurality of output buffer memories for receiving in rotation successive blocks of data at a receiver clock rate equal to said transmission clock rate F TX , means responsive to said data clock rate code for generating output clock pulses at a rate equal to said data clock rate, F n , and means responsive to said output clock pulses and said identification code decoding means for reading out a block of data from a previously filled output buffer memory each time a received block of data is routed to an output buffer memory.
Claim 4
Dependent Claim
68 words
An asynchronous multiplexer as defined in claim 2 wherein said means in each source port for generating said data clock rate code includes means for counting clock pulses having a predetermined frequency relative to said clock rate F TX for a period from a previous interrupt signal to the interrupt signal generated in response to a block of data stored in a buffer memory of the source port.
Claim 5
Dependent Claim
28 words
An asynchronous multiplexer as defined in claim 3 wherein said frequency is related to said clock rate F TX by a factor that is a predetermined whole number.
Claim 6
Dependent Claim
63 words
An asynchronous multiplexer as defined in claim 4 wherein said means for generating output clock pulses at a rate equal to said data clock rate, F n , in each destination port includes means responsive to said data clock rate code for generating said output clock pulses by repeatedly counting down a number equal to said code divided by a predetermined whole number.
Claim 7
Dependent Claim
58 words
An asynchronous multiplexer as defined in claim 5 wherein divisions in said means for generating said output clock pulses are effected by providing a down counter having a number of digit stages less than the number of digits in said data clock rate code for repeatedly entering only the most significant digits of said code for count down.
Claim 8
Dependent Claim
55 words
An asynchronous multiplexer as defined in claim 6 wherein digits of said code not entered into said down counter are added to the content of an accumulator each time said down counter is loaded, and means responsive to any carry from said accumulator for adding said carry to said code entered into said down counter.
Claim 9
Dependent Claim
277 words
An asynchronous multiplexer-demultiplexer for pulse-coded data transmission from a plurality of source ports to a corresponding number of destination ports over a single communication link from a transmitter to a receiver at a predetermined transmitter clock pulse rate sufficiently high to accommodate all of the source ports and corresponding destination ports, each source port comprising a plurality of buffer memories for accumulation of data blocks to be transmitted, means for encoding the data source clock rate into a multi-bit code word, means for generating an interrupt signal to the transmitter, priority interrupt means responsive to the interrupt signals from all of the source ports as they occur for controlling the transmitter to transmit blocks of data from the source ports on a predetermined order of priority giving sources of higher data rate higher priority, means for including in each block of data transmitted a header which includes a multi-bit code word and a source port identification code, means in the receiver for decoding the identification code in each block of data to enable the header of the block of data to be routed to a destination port, means in each destination port for storing a block of data routed to the destination port in one of a plurality of buffer memories in rotation, means in each destination port for decoding the multi-bit code word in the block of data routed to the destination port and producing output clock pulses at a rate for reading out data from one of the buffer memories of the destination port, and means for selecting buffer memories to be read out one at a time on a first in, first out basis.
Claim 10
Dependent Claim
277 words
An asynchronous multiplexer-demultiplexer for pulse-coded data transmission from a plurality of source ports to a corresponding number of destination ports over a single communication link from a transmitter to a receiver at a predetermined transmitter clock pulse rate sufficiently high to accommodate all of the source ports and corresponding destination ports, each source port comprising a plurality of buffer memories for accumulation of data blocks to be transmitted, means for encoding the data source clock rate into a multi-bit code word, means for generating an interrupt signal to the transmitter, priority interrupt means responsive to the interrupt signals from all of the source ports as they occur for controlling the transmitter to transmit blocks of data from the source ports on a predetermined order of priority giving sources of higher data rate higher priority, means for including in each block of data transmitted a header which includes a multi-bit code word and a source port identification code, means in the receiver for decoding the identification code in each block of data to enable the header of the block of data to be routed to a destination port, means in each destination port for storing a block of data routed to the destination port in one of a plurality of buffer memories in rotation, means in each destination port for decoding the multi-bit code word in the block of data routed to the destination port and producing output clock pulses at a rate for reading out data from one of the buffer memories of the destination port, and means for selecting buffer memories to be read out one at a time on a first in, first out basis.
Claim 11
Dependent Claim
71 words
An asynchronous multiplexer-demultiplexer as defined in claim 8 wherein said means for encoding the data clock rate into a multi-bit word in each source port includes means for counting clock pulses having a predetermined frequency relative to the transmitter clock pulse rate for a period from a previous interrupt signal to the interrupt signal generated in response to a block of data stored in a buffer memory of the source port.
Claim 12
Dependent Claim
52 words
An asynchronous multiplexer-demultiplexer as defined in claim 9 wherein said means in each destination port for decoding the multi-bit code word includes means responsive to said multi-bit code word for generating said output clock pulses by repeatedly counting down a number equal to said code word divided by a predetermined whole number.
References Cited (Backward Citations)
US3466397A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-07-03 | 1982-01-02 | 1982-07-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-07-03 | 1986-01-02 | 1986-07-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-07-03 | 1990-01-02 | 1990-07-04 | $7700.00 | Window Closed / Lapsed |