US4114140A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Verification checking system
Assignee: TANKNOLOGY/ENGINEERED SYSTEMS Inc A CORP OF DE (DBA ENGINEERED SYSTEMS INC)
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Filing: 1977-04-25
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Granted: 1978-09-12
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Expires: 1997-04-25
Abstract
Abstract A system used to provide a verification check of a credit card or credit document includes a large capacity read/write memory having a single binary data bit stored at each address location. The credit card has unique identifying information encoded on it for addressing a specific location in the memory. A readout is provided in response to the insertion of the credit card to indicate whether the card is a valid one or not. To program the memory initially, a provision is made for individually addressing each of the different memory locations and to establish a "valid" or "non-valid" binary data bit storage at each location corresponding to a different credit card. In addition, manually operable addressing switches are provided to change the specific bit stored at any given address subsequent to the initial storage of data in the memory.
Inventors
- 👤 John Kubina
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 05:33
CPC Classifications
G; G07; G07F; G07F7/00; G07F7/08; G06; G06Q; G06Q20/00; G06Q20/38; G06Q20/40; G06Q20/403
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
189 words
A system for providing a verification check of uniquely encoded multi-bit binary words including in combination: read/write memory means having a plurality of address locations therein, each address location storing a single binary bit; address control means operated in response to addressing signals and coupled to said memory means for selecting a particular address location in said memory means for writing data into and reading data from said particular address location; read/write control means coupled to said memory means for controlling the mode of operation of said memory means; gating circuit means having a plurality of inputs and having outputs coupled with said address control means for supplying said addressing signals thereto; settable switch means coupled to selected inputs of said gating circuit means for supplying input signals thereto; circuit means coupled to others of the inputs of said gating circuit means for supplying input signals thereto; and selecting means coupled to said gating circuit means for causing the signals appearing on the outputs of said gating circuit means to be selected from the input signals from said settable switch means or the input signals from said circuit means.
Claim 2
Independent Claim
189 words
A system for providing a verification check of uniquely encoded multi-bit binary words including in combination: read/write memory means having a plurality of address locations therein, each address location storing a single binary bit; address control means operated in response to addressing signals and coupled to said memory means for selecting a particular address location in said memory means for writing data into and reading data from said particular address location; read/write control means coupled to said memory means for controlling the mode of operation of said memory means; gating circuit means having a plurality of inputs and having outputs coupled with said address control means for supplying said addressing signals thereto; settable switch means coupled to selected inputs of said gating circuit means for supplying input signals thereto; circuit means coupled to others of the inputs of said gating circuit means for supplying input signals thereto; and selecting means coupled to said gating circuit means for causing the signals appearing on the outputs of said gating circuit means to be selected from the input signals from said settable switch means or the input signals from said circuit means.
Claim 3
Dependent Claim
17 words
The combination according to claim 1 wherein said gate means comprises a multiple-pole, double-throw switching circuit means.
Claim 4
Dependent Claim
44 words
The combination according to claim 1 wherein said memory means has a single output and produces an output signal thereon corresponding to the binary bit stored at the address location selected therein by the addressing signals on the outputs of said gating circuit means.
Claim 5
Dependent Claim
44 words
The combination according to claim 1 further including initializing circuit means coupled with said read/write control means and said address control means for initially causing said memory means to store binary bits of the same type in all of said plurality of address locations.
Claim 6
Dependent Claim
80 words
The combination according to claim 4 wherein said system further includes "set" control means coupled with said read/write control means and said selecting means for causing said memory to be placed in its "write" mode of operation and for causing said gate means to supply addressing signals to said address control means from said settable switch means; and means for causing binary bits having a predetermined binary characteristic to be stored in said memory means at the selected address locations.
Claim 7
Dependent Claim
53 words
The combination according to claim 5 wherein said selecting means further includes means for causing said memory means to operate as a read-only memory means when said selecting means causes said gating circuit means to provide addressing signals on the outputs thereof in response to input signals applied thereto from said circuit means.
Claim 8
Dependent Claim
114 words
The combination according to claim 6 further including a source of clock pulses, and wherein said circuit means includes a jam input counter, the outputs of which are coupled to said others of the inputs of said gating circuit means and the inputs to which are coupled with a source of uniquely encoded multi-bit binary words; and wherein said initializing circuit means causes said counter to be reset to a predetermined initial count and to be operated as a binary pulse counter in response to clock pulses from said clock circuit means until the number of clock pulses counted thereby is at least equal to the number of memory locations in said memory means.
Claim 9
Dependent Claim
37 words
The combination according to claim 7 wherein said settable switch means comprise digital switches capable of being encoded to produce multi-bit binary words having the same number of bits therein as said uniquely encoded multi-bit binary words.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-09-11 | 1982-03-13 | 1982-09-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-09-11 | 1986-03-13 | 1986-09-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-09-11 | 1990-03-13 | 1990-09-12 | $7700.00 | Window Closed / Lapsed |