US4115797A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated injection logic with heavily doped injector base self-aligned with injector emitter and collector
Assignee: Fairchild Semiconductor Corp
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Filing: 1976-10-04
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Granted: 1978-09-19
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Expires: 1996-10-04
Abstract
Abstract An integrated injection logic semiconductor structure having a double diffused lateral PNP transistor and an inverted vertical NPN transistor includes an extended region of epitaxial silicon doped N type by introduction of suitable impurity from two separate regions of the semiconductor surface. This extended N type region, which functions as the base of the PNP transistor, allows an adjoining P type region, which in prior art structures served only as the collector, to be utilized as both the collector and the collector contact, thereby reducing the size of the semiconductor structure. Said N type region substantially lessens the series resistance between the base of the NPN transistor and the collector of the PNP transistor, to thereby facilitate manufacture of integrated injection logic circuits operating faster, at higher current levels, and at higher gain than integrated injection logic circuits not utilizing this invention. The extended N type region also facilitates the manufacture of faster multiple collector integrated circuit structures. Additionally, this invention will be useful in fabricating a more compact double diffused lateral transistor structure.
Inventors
- 👤 Hemraj K. Hingarh
- 👤 Richard E. Crippen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 23:24
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/17; H10D62/177; H10D84/00; H10D84/01; H10D84/0112; H10D84/0116; H10D84/02; H10D84/03; H10D84/038; H10D84/60; H10D84/65; H10P; H10P76/00; H10P76/40; Y; Y10; Y10S; Y10S148/00; Y10S148/087
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
284 words
An integrated injection logic circuit having improved current characteristics comprising: a semiconductor material having at least one substantially flat surface, a lateral transistor having an emitter of first conductivity type formed in a first portion of said semiconductor material adjacent said at least one surface, a base of opposite conductivity type to the emitter formed in a second portion of said semiconductor material adjacent said at least one surface, a collector of first conductivity type formed in a third portion of said semiconductor material adjacent said at least one surface, said second portion being laterally disposed between the first portion and the third portion, said second portion being formed by the diffusion of opposite conductivity type impurity into a first region of the surface and into a second region of the surface, the first and second regions being non-contiguous; a vertical transistor having a second collector of opposite conductivity type to the collector of the lateral transistor defined by a fourth portion of said semiconductor material adjacent said at least one surface, a second base of first conductivity type defined by a fifth portion of said semiconductor material underlying said fourth portion, and a second emitter of opposite conductivity type to the second base defined by a sixth portion of said semiconductor material underlying said fifth portion and spaced from said fourth portion by said fifth portion; said collector of said lateral transistor being formed subsequent to formation of said lateral transistor base and providing a low resistance current path to said base of said vertical transistor; means for electrically contacting said first emitter, first base and first collector; and means for electrically contacting said second emitter, said second base and said second collector.
Claim 2
Dependent Claim
284 words
An integrated injection logic circuit having improved current characteristics comprising: a semiconductor material having at least one substantially flat surface, a lateral transistor having an emitter of first conductivity type formed in a first portion of said semiconductor material adjacent said at least one surface, a base of opposite conductivity type to the emitter formed in a second portion of said semiconductor material adjacent said at least one surface, a collector of first conductivity type formed in a third portion of said semiconductor material adjacent said at least one surface, said second portion being laterally disposed between the first portion and the third portion, said second portion being formed by the diffusion of opposite conductivity type impurity into a first region of the surface and into a second region of the surface, the first and second regions being non-contiguous; a vertical transistor having a second collector of opposite conductivity type to the collector of the lateral transistor defined by a fourth portion of said semiconductor material adjacent said at least one surface, a second base of first conductivity type defined by a fifth portion of said semiconductor material underlying said fourth portion, and a second emitter of opposite conductivity type to the second base defined by a sixth portion of said semiconductor material underlying said fifth portion and spaced from said fourth portion by said fifth portion; said collector of said lateral transistor being formed subsequent to formation of said lateral transistor base and providing a low resistance current path to said base of said vertical transistor; means for electrically contacting said first emitter, first base and first collector; and means for electrically contacting said second emitter, said second base and said second collector.
Claim 3
Dependent Claim
33 words
Structure as in claim 1 wherein: the first, third, and fifth portions of semiconductor material are P conductivity type, and the second, fourth, and sixth portions of semiconductor material are N conductivity type.
Claim 4
Dependent Claim
33 words
Structure as in claim 1 wherein: the first, third, and fifth portions of semiconductor material are N conductivity type, and the second, fourth, and sixth portions of semiconductor material are P conductivity type.
Claim 5
Dependent Claim
16 words
Structure as in claim 1 wherein the second portion is electrically connected to the fourth portion.
Claim 6
Dependent Claim
53 words
Structure as in claim 1 wherein the means for contacting the second emitter comprises a second conducting channel which contacts the second emitter within the semiconductor material and provides electrical communication with the surface at a region separated from each of the first emitter, base, collector second emitter, second base, and second collector.
Claim 7
Dependent Claim
43 words
Structure as in claim 5 wherein the second conducting channel comprises: a second buried layer of semiconductor material connecting the second emitter to the base, and a second sink of semiconductor material connecting said second buried layer to the at least one surface.
Claim 8
Dependent Claim
31 words
Structure as in claim 6 wherein a second closed path of semiconductor material surrounding the structure is oxidized to extend between the second buried layer and the at least one surface.
Claim 9
Dependent Claim
48 words
Structure as in claim 7 wherein: the second buried layer, the second sink, the base, and each of the at least one second collectors are N type semiconductor material, and the emitter, the collector, and each of the at least one second bases are P type semiconductor material.
Claim 10
Dependent Claim
48 words
Structure as in claim 8 wherein: the second buried layer, the second sink, the base, and each of the at least one second collectors are P type semiconductor material, and the emitter, the collector, and each of the at least one second bases are N type semiconductor material.
Claim 11
Independent Claim
210 words
A method of forming a lateral transistor semiconductor structure comprising: forming an isolated pocket of semiconductor material in a substrate having a substantially flat upper surface, the upper surface of said isolated pocket being divided into a first and a second region, forming a region of masking material over selected portions of said first region, introducing first impurity of one conductivity type into the pocket from two non-contiguous regions of the flat surface adjacent the region of masking material, and allowing the first impurity introduced into the other of said regions to contact the first impurity introduced into the other of said regions, introducing second impurity of opposite conductivity to the first impurity into the two non-contiguous regions and into the second region of the upper surface, the second impurity introduced into either of the two non-contiguous regions not being in contact with the second impurity introduced into the other of the two non-contiguous regions, introducing first impurity into selected portions of the second region; and wherein the step of introducing second impurity includes introducing second impurity into all of the second region, subsequently introducing second impurity into each of the two non-contiguous regions in the first region, and into all of the second region, except for said selected portions.
Claim 12
Independent Claim
210 words
A method of forming a lateral transistor semiconductor structure comprising: forming an isolated pocket of semiconductor material in a substrate having a substantially flat upper surface, the upper surface of said isolated pocket being divided into a first and a second region, forming a region of masking material over selected portions of said first region, introducing first impurity of one conductivity type into the pocket from two non-contiguous regions of the flat surface adjacent the region of masking material, and allowing the first impurity introduced into the other of said regions to contact the first impurity introduced into the other of said regions, introducing second impurity of opposite conductivity to the first impurity into the two non-contiguous regions and into the second region of the upper surface, the second impurity introduced into either of the two non-contiguous regions not being in contact with the second impurity introduced into the other of the two non-contiguous regions, introducing first impurity into selected portions of the second region; and wherein the step of introducing second impurity includes introducing second impurity into all of the second region, subsequently introducing second impurity into each of the two non-contiguous regions in the first region, and into all of the second region, except for said selected portions.
Claim 13
Dependent Claim
22 words
A method as in claim 10 wherein the first impurity is N conductivity type and the second impurity is P conductivity type.
Claim 14
Dependent Claim
22 words
A method as in claim 10 wherein the first impurity is N conductivity type and the second impurity is P conductivity type.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-09-18 | 1982-03-20 | 1982-09-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-09-18 | 1986-03-20 | 1986-09-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-09-18 | 1990-03-20 | 1990-09-19 | $7700.00 | Window Closed / Lapsed |