Instruction processing control apparatus

Claim 2

In a stored program computer an addressable storage containing data and instructions, said instructions including storage access instructions and register access instructions, instruction decode means connected to receive from said storage storage access and register access instructions and responsive to said storage access instructions for generating storage control signals and responsive to said register access instructions for generating register control signals, a plurality of addressable registers for storing data, a source of addresses, addressing means connected to receive addresses from said source of addresses and selectively operable under control of storage control signals to address said storage and under control of register control signals to address said registers, and means for applying said storage control signals and said register control signals to said addressing means whereby said storage is addressed upon said instruction decode means decoding a storage access instruction and said registers are addressed upon said instruction decode means decoding a register access instruction.

Claim 3

The stored program computer of claim 1 wherein said storage access and said register access instructions have common operation codes and at least one address modification control bit for controlling modification of addresses from said source of addresses, the bit state of said at least one address modification control bit of said register access instruction being opposite to the bit state of said at least one address modification control bit of said storage access instruction so as to provide said instruction decode means with at least one condition for distinguishing a register access instruction from a storage access instruction.

Claim 4

The stored program computer of claim 2 further comprising: means connected to said source of addresses and responsive only to the bit state of said at least one address modification control bit of said storage access instruction to modify an address from said source of addresses and means responsive to said instruction decode means generating a register control signal upon decoding a register access instruction for converting the bit state of said at least one address modification control bit of said register access instruction to the bit state of said at least one address control bit of said storage access instruction.

Claim 5

The stored program computer system of claim 1 wherein the origin of data to be entered into the addressed storage location or the addressed register is specified by local storage register address fields contained in said storage access and register access instructions and further comprising: addressable local storage registers, local storage register addressing means connected to address said local storage registers in response to receiving addresses from said address fields contained in said storage access and register access instructions, and means for selectively transferring addresses from said address fields contained in said storage access and register access instructions to said local storage register addressing means.

Claim 6

In a stored program computer system having addressable storage and addressable registers, a source of addresses, addressing means connected to receive addresses from said source of addresses and selectively operable to address said addressable storage or said addressable registers, circuitry for incrementing or decrementing addresses from said source of addresses, said system including storage control and register control instructions stored at addressable locations in said addressable storage, said register control and storage control instructions each having a plurality of bits with storage control instruction decode circuitry responsive to storage control instructions and register control instructions for generating storage control signals, the improvement comprising register control instruction decode apparatus connected to receive at least one of said storage control signals generated by said storage control instruction decode circuitry and responsive to said at least one of said storage control signals generated by said storage control instruction decode circuitry and to predetermined bits in said register control instruction to generate a signal for causing said addressing means to address said addressable registers instead of said addressable storage.

Claim 7

In a stored program computer system having addressable storage and addressable registers, a source of addresses, addressing means connected to receive addresses from said source of addresses and selectively operable to address said addressable storage or said addressable registers, circuitry for incrementing or decrementing addresses from said source of addresses, said system including storage control and register control instructions stored at addressable locations in said addressable storage, said register control and storage control instructions each having a plurality of bits with storage control instruction decode circuitry responsive to storage control instructions and register control instructions for generating storage control signals, the improvement comprising register control instruction decode apparatus connected to receive at least one of said storage control signals generated by said storage control instruction decode circuitry and responsive to said at least one of said storage control signals generated by said storage control instruction decode circuitry and to predetermined bits in said register control instruction to generate a signal for causing said addressing means to address said addressable registers instead of said addressable storage.

Claim 8

The computer system of claim 5 further comprising: means for converting the state of one of said predetermined bits and feeding the converted bit back into said storage control instruction decode circuitry to cause the same to generate address increment or address decrement signals depending upon the state of the converted bit.

Claim 9

In a stored program computer system having addressable storage and addressable registers, a source of addresses, addressing means connected to receive addresses from said source of addresses and selectively operable to address said addressable storage or said addressable registers, circuitry for incrementing or decrementing addresses from said source of addresses, said system including control instructions stored at addressable locations in said addressable storage and having at least one bit where said one bit can be in a first or second state for controlling selective operation of said addressing means, the improvement comprising: instruction decode means responsive to said at least one bit in said control instructions to cause said addressing means to address said addressable register instead of said addressable storage when said at least one bit is in said first state and to cause said addressing means to address said addressable storage instead of said addressable registers when said at least one bit is in said second state.

Claim 10

In a stored program computer system having addressable storage and addressable registers, a source of addresses, addressing means connected to receive addresses from said source of addresses and selectively operable to address said addressable storage or said addressable registers, circuitry for incrementing or decrementing addresses from said source of addresses, said system including control instructions stored at addressable locations in said addressable storage and having at least one bit where said one bit can be in a first or second state for controlling selective operation of said addressing means, the improvement comprising: instruction decode means responsive to said at least one bit in said control instructions to cause said addressing means to address said addressable register instead of said addressable storage when said at least one bit is in said first state and to cause said addressing means to address said addressable storage instead of said addressable registers when said at least one bit is in said second state.

Claim 11

The computer system of claim 7 wherein said circuitry for incrementing or decrementing addresses is connected to operate under control of said at least one bit being in said second state.

Claim 12

The computer system of claim 8 further comprising: means for converting the state of said at least one bit from said first to said second state to enable address incrementing or decrementing during the register addressing operation.