Regenerator circuit for CCD arrangements

Claim 2

Regenerator circuit for CCD arrangements for connecting a first CCD arrangement having an output diffusion zone to a second CCD arrangement, said output diffusion zone having a capacitance to ground during operation, said second CCD arrangement having an input diffusion zone, said input diffusion zone having a capacitance to ground during operation, a first input transistor being formed by said input diffusion zone, a gate electrode adjacent said input diffusion zone and a potential well which lies below the next adjacent electrode of said second CCD arrangement, said output diffusion zone being connected via a connection line to said gate electrode of said input transistor, and having a first load element which on the one hand is connected to said output diffusion zone and on the other hand to a first control line to which a first potential with an amplitude having a first value can be connected, a second load element being provided which on the one hand is connected to said first control line and on the other hand to a third load element, said third load element being connected on the one hand to said second load element and on the other hand to said input diffusion zone of said second CCD arrangement, a capacitor coupling said first control line to said input diffusion zone of said second CCD arrangement, a second transistor being connected on the one hand to said input diffusion zone and on the other hand to a second control line to which ground potential can be connected, and the gate terminal of said second transistor being connected to a third control line to which a second potential having a second value can be connected, the capacitance of the coupling capacitor being determined in accordance with the formula: ##EQU2## where: C 46 is the value of said coupling capacitor; C 33 is the capacitance between the input diffusion zone and ground; U R is the amplitude of the voltage pulses in said first control line; U A is the value of the charges stored by the capacitance formed between the output diffusion zone and ground; ΔU A is the value of the charge arriving at said output diffusion zone divided by the output capacitance formed between the output diffusion zone and ground; and

Claim 3

δ U is ΔU A divided by 2, which arises when a charge is transmitted to the output diffusion zone.

Claim 4

δ U is ΔU A divided by 2, which arises when a charge is transmitted to the output diffusion zone.

Claim 5

The combination according to claim 1 comprising additionally a plurality of first charge coupled device arrangements each having an associated first capacitance, corresponding to an output diffusion zone, and a plurality of second charge coupled device arrangements each having an associated second capacitance, corresponding to an input diffusion zone, arranged such that for each of said first charge coupled device arrangements there exists a corresponding one of said second charge coupled device arrangements; said regenerator circuit having an individual charging means associated with each of said first capacitances and a common charging means for all of said second capacitances causing a selected charge to be regenerated for a selected input/output charge coupled device pair.

Claim 6

A regeneragor circuit for a plurality of pairs of input CCDs and output CCDs in which one CCD of each pair is coupled to the other CCD of the same pair in accordance with claim 1, wherein said coupling capacitor, said second transistor and said control lines are common to all of said pairs.

Claim 7

A regenerator circuit as set forth in claim 1, which includes a plurality of input stages, a centralized regenerator circuit, the input diffusion zone of said second CCDs being electrically connected to one another, and each being connected by a pulse clock drive line to said centralized regenerator circuit, and in which each of said pulse clock drive lines are connected by load elements to said output diffusion zones of said first CCDs.

Claim 8

Regenerator circuit for CCD arrangements for connecting a first CCD arrangement having an output diffusion zone to a second CCD arrangement, said output diffusion zone having a capacitance to ground during operation, said second CCD arrangement having an input diffusion zone, said input diffusion zone having a capacitance to ground during operation, a first input transistor being formed by said input diffusion zone, a gate electrode adjacent said input diffusion zone and a potential well which lies below the next adjacent electrode of said second CCD arrangement, said output diffusion zone being connected via a connection line to said gate electrode of said input transistor, a first load transistor having source, drain and gate electrodes, said source electrode being connected to said output diffusion zone, a first control line to which a first clock pulse potential with an amplitude having a first value being connected to said gate electrode of said first load transistor, a second load transistor having source, drain and gate electrodes, said gate and drain electrodes of said second transistor being connected to said drain electrode of said first load transistor, a second control line to which a clock pulse potential with an amplitude having a second value being connected to the common drain electrode connection of the first and second load transistors, a capacitor coupling said second control line to said input diffusion zone, a third load transistor having source, drain and gate electrodes, said source electrode of said third load transistor being connected to said second control line and said gate electrode of said third load transistor being connected to an additional third control line, the capacitance of the coupling capacitor being determined in accordance with the formula: ##EQU3## where: C 56 is the capacitance of said coupling capacitor; C 33 is the capacitance between the input diffusion zone and ground; U R2 is the amplitude of the voltage pulses in said second control line; U A is the value of the charges stored by the capacitance formed between the output diffusion zone and ground; ΔU A is the value of the charge arriving at said output diffusion zone divided by the output capacitance formed between the output diffusion zone and ground; and δ U is ΔU A divided by 2, which arises when a charge is transmitted to the output diffusion zone.

Claim 9

Regenerator circuit for CCD arrangements for connecting a first CCD arrangement having an output diffusion zone to a second CCD arrangement, said output diffusion zone having a capacitance to ground during operation, said second CCD arrangement having an input diffusion zone, said input diffusion zone having a capacitance to ground during operation, a first input transistor being formed by said input diffusion zone, a gate electrode adjacent said input diffusion zone and a potential well which lies below the next adjacent electrode of said second CCD arrangement, said output diffusion zone being connected via a connection line to said gate electrode of said input transistor, a first load transistor having source, drain and gate electrodes, said source electrode being connected to said output diffusion zone, a first control line to which a first clock pulse potential with an amplitude having a first value being connected to said gate electrode of said first load transistor, a second load transistor having source, drain and gate electrodes, said gate and drain electrodes of said second transistor being connected to said drain electrode of said first load transistor, a second control line to which a clock pulse potential with an amplitude having a second value being connected to the common drain electrode connection of the first and second load transistors, a capacitor coupling said second control line to said input diffusion zone, a third load transistor having source, drain and gate electrodes, said source electrode of said third load transistor being connected to said second control line and said gate electrode of said third load transistor being connected to an additional third control line, the capacitance of the coupling capacitor being determined in accordance with the formula: ##EQU3## where: C 56 is the capacitance of said coupling capacitor; C 33 is the capacitance between the input diffusion zone and ground; U R2 is the amplitude of the voltage pulses in said second control line; U A is the value of the charges stored by the capacitance formed between the output diffusion zone and ground; ΔU A is the value of the charge arriving at said output diffusion zone divided by the output capacitance formed between the output diffusion zone and ground; and δ U is ΔU A divided by 2, which arises when a charge is transmitted to the output diffusion zone.

Claim 10

A regenerator circuit for a plurality of pairs of input CCDs and output CCDs in which one CCD of each pair is coupled to the other CCD of the same pair in accordance with claim 5, wherein said second load transistor, said third load transistor, said first, second and third control lines and said coupling capacitor are common to all of said pairs.

Claim 11

A regenerator circuit as set forth in claim 5, which includes a plurality of input stages, a centralized regenerator circuit, the input diffusion zone of said second CCDs being electrically connected to one another, and each being connected by a pulse clock drive line to said centralized regenerator circuit, and in which each of said pulse clock drive lines are connected by load transistors to said output diffusion zones of said first CCDs.

Claim 12

Regenerator circuit for CCD arrangements for connecting a first CCD arrangement having an output diffusion zone to a second CCD arrangement, said output diffusion zone having a capacitance to ground during operation, said second CCD arrangement having an input diffusion zone, said input diffusion zone having a capacitance to ground during operation, a first input transistor being formed by said input diffusion zone, a gate electrode adjacent said input diffusion zone and a potential well which lies below the next adjacent electrode of said second CCD arrangement, said output diffusion zone being connected via a connection line to said gate electrode of said input transistor, a first load element which on the one hand is connected to said output diffusion zone and on the other hand to a first control line to which a first clock pulse potential can be connected, a second load element being provided which on the one hand is connected to said first control line and on the other hand to a third load element, said third load element being connected on the one hand to said second load element and on the other hand to said input diffusion zone of said second CCD arrangement, a capacitor coupling said first control line to said input diffusion zone of said second CCD arrangement, a second control line to which a clock pulse potential can be connected, a second transistor connected on the one hand to said input diffusion zone of said second CCD arrangement and on the other hand to said first control line, said gate terminal of said second transistor being connected to said second control line, the capacitance of the coupling capacitor being determined in accordance with the formula: ##EQU4## where: C 66 is the capacitance of said coupling capacitor; C 33 is the capacitance between the input diffusion zone and ground; U R is the amplitude of the voltage pulses in said first control line; U A is the value of the charges stored by the capacitance formed between the output diffusion zone and ground; ΔU A is the value of the charge arriving at said output diffusion zone divided by the output capacitance formed between the output diffusion zone and ground; and δ U is ΔU A divided by 2, which arises when a charge is transmitted to the output diffusion zone.

Claim 13

Regenerator circuit for CCD arrangements for connecting a first CCD arrangement having an output diffusion zone to a second CCD arrangement, said output diffusion zone having a capacitance to ground during operation, said second CCD arrangement having an input diffusion zone, said input diffusion zone having a capacitance to ground during operation, a first input transistor being formed by said input diffusion zone, a gate electrode adjacent said input diffusion zone and a potential well which lies below the next adjacent electrode of said second CCD arrangement, said output diffusion zone being connected via a connection line to said gate electrode of said input transistor, a first load element which on the one hand is connected to said output diffusion zone and on the other hand to a first control line to which a first clock pulse potential can be connected, a second load element being provided which on the one hand is connected to said first control line and on the other hand to a third load element, said third load element being connected on the one hand to said second load element and on the other hand to said input diffusion zone of said second CCD arrangement, a capacitor coupling said first control line to said input diffusion zone of said second CCD arrangement, a second control line to which a clock pulse potential can be connected, a second transistor connected on the one hand to said input diffusion zone of said second CCD arrangement and on the other hand to said first control line, said gate terminal of said second transistor being connected to said second control line, the capacitance of the coupling capacitor being determined in accordance with the formula: ##EQU4## where: C 66 is the capacitance of said coupling capacitor; C 33 is the capacitance between the input diffusion zone and ground; U R is the amplitude of the voltage pulses in said first control line; U A is the value of the charges stored by the capacitance formed between the output diffusion zone and ground; ΔU A is the value of the charge arriving at said output diffusion zone divided by the output capacitance formed between the output diffusion zone and ground; and δ U is ΔU A divided by 2, which arises when a charge is transmitted to the output diffusion zone.

Claim 14

A regenerator circuit for a plurality of pairs of input CCDs and output CCDs in which one CCD of each pair is coupled to the other CCD of the same pair in accordance with claim 8, wherein said coupling capacitor, said first and second control lines said second and third load elements and said second transistor are common to all of said pairs.

Claim 15

A regenerator circuit as set forth in claim 8, which includes a plurality of input stages, a centralized regenerator circuit, the input diffusion zone of said second CCDs being electrically connected to one another, and each being connected by a pulse clock drive line to said centralized regenerator circuit, and in which each of said pulse clock drive lines are connected by load elements to said output diffusion zones of said first CCDs.

Claim 16

Regenerator circuit for CCD arrangements for connecting a first CCD arrangement having an output diffusion zone to a second CCD arrangement, said output diffusion zone having a capacitance to ground during operation, said second CCD arrangement having an input diffusion zone, said input diffusion zone having a capacitance to ground during operation, a first input transistor being formed by said input diffusion zone, a gate electrode adjacent said input diffusion zone and a potential well which lies below the next adjacent electrode of said second CCD arrangement, said output diffusion zone being connected via a connection line to said gate electrode of said input transistor, a first load element which on the one hand is connected to said output diffusion zone and on the other hand to a first control line to which a first clock pulse potential can be connected, a second load element being provided which on the one hand is connected to said first control line and on the other hand to a third load element, said third load element being connected on the one hand to said second load element and on the other hand to said input diffusion zone of said second CCD arrangement, a capacitor coupling a second control line to which a second clock pulse potential can be coupled to said input diffusion zone of said second CCD arrangement, a second transistor having source, drain and gate electrodes connected on the one hand to said input diffusion zone and on the other hand to ground, a third control line to which a clock pulse potential can be connected, said third control line being connected to said gate electrode of said second transistor, the capacitance of the coupling capacitor being determined in accordance with the formula: ##EQU5## where: C 75 is the capacitance of said coupling capacitor; C 33 is the capacitance between the input diffusion zone and ground; U C is the amplitude of the voltage pulses in said second control line; U A is the value of the charges stored by the capacitance formed between the output diffusion zone and ground; ΔU A is the value of the charge arriving at said output diffusion zone divided by the output capacitance formed between the output diffusion zone and ground; and δ U is ΔU A divided by 2, which arises when a charge is transmitted to the output diffusion zone.

Claim 17

Regenerator circuit for CCD arrangements for connecting a first CCD arrangement having an output diffusion zone to a second CCD arrangement, said output diffusion zone having a capacitance to ground during operation, said second CCD arrangement having an input diffusion zone, said input diffusion zone having a capacitance to ground during operation, a first input transistor being formed by said input diffusion zone, a gate electrode adjacent said input diffusion zone and a potential well which lies below the next adjacent electrode of said second CCD arrangement, said output diffusion zone being connected via a connection line to said gate electrode of said input transistor, a first load element which on the one hand is connected to said output diffusion zone and on the other hand to a first control line to which a first clock pulse potential can be connected, a second load element being provided which on the one hand is connected to said first control line and on the other hand to a third load element, said third load element being connected on the one hand to said second load element and on the other hand to said input diffusion zone of said second CCD arrangement, a capacitor coupling a second control line to which a second clock pulse potential can be coupled to said input diffusion zone of said second CCD arrangement, a second transistor having source, drain and gate electrodes connected on the one hand to said input diffusion zone and on the other hand to ground, a third control line to which a clock pulse potential can be connected, said third control line being connected to said gate electrode of said second transistor, the capacitance of the coupling capacitor being determined in accordance with the formula: ##EQU5## where: C 75 is the capacitance of said coupling capacitor; C 33 is the capacitance between the input diffusion zone and ground; U C is the amplitude of the voltage pulses in said second control line; U A is the value of the charges stored by the capacitance formed between the output diffusion zone and ground; ΔU A is the value of the charge arriving at said output diffusion zone divided by the output capacitance formed between the output diffusion zone and ground; and δ U is ΔU A divided by 2, which arises when a charge is transmitted to the output diffusion zone.

Claim 18

A regenerator circuit for a plurality of pairs of input CCDs and output CCDs in which one CCD of each pair is coupled to the other CCD of the same pair in accordance with claim 11, wherein said second and third load elements, said second transistor, said coupling capacitor and said first, second and third control lines are common to all of said pairs.

Claim 19

A regenerator circuit as set forth in claim 11, which includes a plurality of input stages, a centralized regenerator circuit, the input diffusion zone of said second CCDs being electrically connected to one another, and each being connected by a pulse clock drive line to said centralized regenerator circuit, and in which, each of said pulse clock drive lines are connected by load elements to said output diffusion zones of said first CCDs.

Claim 20

Regenerator circuit for CCD arrangements for connecting a first CCD arrangement having an output diffusion zone to a second CCD arrangement, said output diffusion zone having a capacitance to ground during operation, said second CCD arrangement having an input diffusion zone, said input diffusion zone having a capacitance to ground during operation, a first input transistor being formed by said input diffusion zone, a gate electrode adjacent said input diffusion zone and a potential well which lies below the next adjacent electrode of said second CCD arrangement, said output diffusion zone being connected via a connection line to said gate electrode of said input transistor, first, second and third clock pulse potential control lines, a fourth control line to which ground potential can be connected, a first load element which on the one hand is connected to said output diffusion zone and on the other hand to said first control line, a second load element being provided which on the one hand is connected to said second control line and on the other hand to a third load element, said third load element being connected on the one hand to said second load element and on the other hand to said input diffusion zone of said second CCD arrangement, a second transistor connected between said fourth control line and said input diffusion zone, and the gate terminal of said second transistor being connected to said third control line.

Claim 21

Regenerator circuit for CCD arrangements for connecting a first CCD arrangement having an output diffusion zone to a second CCD arrangement, said output diffusion zone having a capacitance to ground during operation, said second CCD arrangement having an input diffusion zone, said input diffusion zone having a capacitance to ground during operation, a first input transistor being formed by said input diffusion zone, a gate electrode adjacent said input diffusion zone and a potential well which lies below the next adjacent electrode of said second CCD arrangement, said output diffusion zone being connected via a connection line to said gate electrode of said input transistor, first, second and third clock pulse potential control lines, a fourth control line to which ground potential can be connected, a first load element which on the one hand is connected to said output diffusion zone and on the other hand to said first control line, a second load element being provided which on the one hand is connected to said second control line and on the other hand to a third load element, said third load element being connected on the one hand to said second load element and on the other hand to said input diffusion zone of said second CCD arrangement, a second transistor connected between said fourth control line and said input diffusion zone, and the gate terminal of said second transistor being connected to said third control line.

Claim 22

A regenerator circuit for a plurality of pairs of inputs CCDs and output CCDs in which one CCD of each pair is coupled to the other CCD of the same pair in accordance with claim 14, wherein said first, second, third and fourth control lines, said second and third load elements and said second transistor are common to all of said pairs.

Claim 23

Regenerator circuit for CCD arrangements for connecting a first CCD arrangement having an output diffusion zone to a second CCD arrangement, said output diffusion zone having a capacitance to ground during operation, said second CCD arrangement having an input diffusion zone, said input diffusion zone having a capacitance to ground during operation, a first input transistor being formed by said input diffusion zone, a gate electrode adjacent said input diffusion zone and a potential well which lies below the next adjacent electrode of said second CCD arrangement, said output diffusion zone being connected via a connection line to said gate electrode of said input transistor, first, second, third and fourth control lines to which clock pulse potentials can be connected, and a fifth control line to which a ground potential can be connected, a second transistor having its channel connected between said output diffusion zone and said first control line and having its gate electrode connected to said second control line, a third transistor having its channel connected between said third control line and said input diffusion zone of said second CCD arrangement, the gate of said third transistor being connected to said third control line, a fourth transistor having its channel connected between said fifth control line and said input diffusion zone of said second CCD arrangement and its gate electrode connected to said fourth control line.

Claim 24

Regenerator circuit for CCD arrangements for connecting a first CCD arrangement having an output diffusion zone to a second CCD arrangement, said output diffusion zone having a capacitance to ground during operation, said second CCD arrangement having an input diffusion zone, said input diffusion zone having a capacitance to ground during operation, a first input transistor being formed by said input diffusion zone, a gate electrode adjacent said input diffusion zone and a potential well which lies below the next adjacent electrode of said second CCD arrangement, said output diffusion zone being connected via a connection line to said gate electrode of said input transistor, first, second, third and fourth control lines to which clock pulse potentials can be connected, and a fifth control line to which a ground potential can be connected, a second transistor having its channel connected between said output diffusion zone and said first control line and having its gate electrode connected to said second control line, a third transistor having its channel connected between said third control line and said input diffusion zone of said second CCD arrangement, the gate of said third transistor being connected to said third control line, a fourth transistor having its channel connected between said fifth control line and said input diffusion zone of said second CCD arrangement and its gate electrode connected to said fourth control line.

Claim 25

A regenerator circuit for a plurality of pairs of input CCDs and output CCDs in which one CCD of each pair is coupled to the other CCD of the same pair in accordance with claim 16, wherein said first, second, third, fourth and fifth control lines, said third and fourth transistors are common to all of said pairs.

Claim 26

The combination of two CCD arrangements and a regenerator circuit comprising a first and second CCD arrangement; a first capacitance and means to charge said first capacitance to a predetermined potential; a second capacitance and means to charge said second capacitance to a predetermined potential; means to detect the absence of charge at the output terminal of said first CCD arrangement and not discharging said first capacitance, gate means at the input to said second CCD arrangement detecting the presence of charge on said first capacitance and the injection of charge from said second capacitance into the input terminal of said second CCD arrangement being permitted; means to detect the presence of charge at said output terminal of said first CCD arrangement and discharge said first capacitance, said gate means detecting the absence of charge on said first capacitance and and the injection of charge from said second capacitance into said second CCD arrangement being blocked, said first and second CCD arrangements comprising charge coupled devices having an input terminal and an output terminal; said first and second capacitances comprising capacitances in the output diffusion zone associated with said output terminal of said first charge coupled device and in the input diffusion zone associated with said input terminal of said second charge coupled device, said means to charge said first capacitance comprising a first transistor connected between said first capacitance and a first control potential terminal, said transistor having its gate input connected to said first control potential terminal; wherein said means to charge said second capacitance comprises a circuit mode, a second transistor connected between said first control potential terminal and said circuit node, said second transistor having its gate input connected to said first control potential terminal and a third transistor connected between said circuit node and said second capacitance, said third transistor having its gate input connected to said circuit node; comprising additionally a fourth transistor connected between said second capacitance and a reference potential, said fourth transistor having its gate input connected to a second control potential terminal, and a third capacitance connected between said second capacitance and said first control potential terminal; the value of said third capacitance being determined in accordance with: ##EQU6## where: C 46 is the value of said third capacitance; C 33 is the capacitance between the input diffusion zone and ground; U R is an amplitude of the voltage pulses in said first control line; U A is the value of the charges stored by the capacitance formed between the output diffusion zone and ground; ΔU A is the value of the charge arriving at said output diffusion zone divided by the output capacitance formed between the output diffusion zone and ground; and δ U is ΔU A divided by 2, which arises when a charge is transmitted to the output diffusion zone.

Claim 27

The combination of two CCD arrangements and a regenerator circuit comprising a first and second CCD arrangement; a first capacitance and means to charge said first capacitance to a predetermined potential; a second capacitance and means to charge said second capacitance to a predetermined potential; means to detect the absence of charge at the output terminal of said first CCD arrangement and not discharging said first capacitance, gate means at the input to said second CCD arrangement detecting the presence of charge on said first capacitance and the injection of charge from said second capacitance into the input terminal of said second CCD arrangement being permitted; means to detect the presence of charge at said output terminal of said first CCD arrangement and discharge said first capacitance, said gate means detecting the absence of charge on said first capacitance and and the injection of charge from said second capacitance into said second CCD arrangement being blocked, said first and second CCD arrangements comprising charge coupled devices having an input terminal and an output terminal; said first and second capacitances comprising capacitances in the output diffusion zone associated with said output terminal of said first charge coupled device and in the input diffusion zone associated with said input terminal of said second charge coupled device, said means to charge said first capacitance comprising a first transistor connected between said first capacitance and a first control potential terminal, said transistor having its gate input connected to said first control potential terminal; wherein said means to charge said second capacitance comprises a circuit mode, a second transistor connected between said first control potential terminal and said circuit node, said second transistor having its gate input connected to said first control potential terminal and a third transistor connected between said circuit node and said second capacitance, said third transistor having its gate input connected to said circuit node; comprising additionally a fourth transistor connected between said second capacitance and a reference potential, said fourth transistor having its gate input connected to a second control potential terminal, and a third capacitance connected between said second capacitance and said first control potential terminal; the value of said third capacitance being determined in accordance with: ##EQU6## where: C 46 is the value of said third capacitance; C 33 is the capacitance between the input diffusion zone and ground; U R is an amplitude of the voltage pulses in said first control line; U A is the value of the charges stored by the capacitance formed between the output diffusion zone and ground; ΔU A is the value of the charge arriving at said output diffusion zone divided by the output capacitance formed between the output diffusion zone and ground; and δ U is ΔU A divided by 2, which arises when a charge is transmitted to the output diffusion zone.

Claim 28

The combination of two CCD arrangements and a regenerator circuit comprising a first and second CCD arrangement; a first capacitance and means to charge said first capacitance to a predetermined potential; a second capacitance and means to charge said second capacitance to a predetermined potential; means to detect the absence of charge at the output terminal of said first CCD arrangement and not discharging said first capacitance, gate means at the input to said second CCD arrangement detecting the presence of charge on said first capacitance and the injection of charge from said second capacitance into the input terminal of said second CCD arrangement being permitted; means to detect the presence of charge at said output terminal of said first CCD arrangement and discharge said first capacitance, said gate means detecting the absence of charge on said first capacitance and the injection of charge from said second capacitance into said second CCD arrangement being blocked, said first and second CCD arrangements comprising charge coupled devices having an input terminal and an output terminal; said first and second capacitances comprising capacitances in the output diffusion zone associated with said output terminal of said first charge coupled device and in the input diffusion zone associated with said input terminal of said second charge coupled device, said means to charge said first capacitance comprising a first transistor connected between said first capacitance and a first control potential terminal; wherein said means to charge said second capacitance comprises a second transistor connected between said first control potential terminal and said input terminal to said second charge coupled device; comprising additionally a third transfer connected between said second capacitance and said first control potential terminal, said third transistor having its gate input connected to a second control potential terminal and a third capacitance connected between said second capacitance and said first control potential terminal; the value of said third capacitance being determined in accordance with: ##EQU7## where: C 56 is the capacitance of said third capacitance; C 33 is the capacitance between the input diffusion zone and ground; U R2 is the amplitude of the voltage pulses in said first control line; U A is the value of the charges stored by the capacitance formed between the output diffusion zone and ground; ΔU A is the value of the charge arriving at said output diffusion zone divided by the output capacitance formed between the output diffusion zone and ground; and δ U is ΔU A divided by 2, which arises when a charge is transmitted to the output diffusion zone.

Claim 29

The combination of two CCD arrangements and a regenerator circuit comprising a first and second CCD arrangement; a first capacitance and means to charge said first capacitance to a predetermined potential; a second capacitance and means to charge said second capacitance to a predetermined potential; means to detect the absence of charge at the output terminal of said first CCD arrangement and not discharging said first capacitance, gate means at the input to said second CCD arrangement detecting the presence of charge on said first capacitance and the injection of charge from said second capacitance into the input terminal of said second CCD arrangement being permitted; means to detect the presence of charge at said output terminal of said first CCD arrangement and discharge said first capacitance, said gate means detecting the absence of charge on said first capacitance and the injection of charge from said second capacitance into said second CCD arrangement being blocked, said first and second CCD arrangements comprising charge coupled devices having an input terminal and an output terminal; said first and second capacitances comprising capacitances in the output diffusion zone associated with said output terminal of said first charge coupled device and in the input diffusion zone associated with said input terminal of said second charge coupled device, said means to charge said first capacitance comprising a first transistor connected between said first capacitance and a first control potential terminal; wherein said means to charge said second capacitance comprises a second transistor connected between said first control potential terminal and said input terminal to said second charge coupled device; comprising additionally a third transfer connected between said second capacitance and said first control potential terminal, said third transistor having its gate input connected to a second control potential terminal and a third capacitance connected between said second capacitance and said first control potential terminal; the value of said third capacitance being determined in accordance with: ##EQU7## where: C 56 is the capacitance of said third capacitance; C 33 is the capacitance between the input diffusion zone and ground; U R2 is the amplitude of the voltage pulses in said first control line; U A is the value of the charges stored by the capacitance formed between the output diffusion zone and ground; ΔU A is the value of the charge arriving at said output diffusion zone divided by the output capacitance formed between the output diffusion zone and ground; and δ U is ΔU A divided by 2, which arises when a charge is transmitted to the output diffusion zone.

Claim 30

The combination of two CCD arrangements and a regenerator circuit comprising a first and second CCD arrangement; a first capacitance and means to charge said first capacitance to a predetermined potential; a second capacitance and means to charge said second capacitance to a predetermined potential; means to detect the absence of charge at the output terminal of said first CCD arrangement and not discharging said first capacitance, gate means at the input to said second CCD arrangement detecting the presence of charge on said first capacitance and the injection of charge from said second capacitance into the input terminal of said second CCD arrangement being permitted; means to detect the presence of charge at said output terminal of said first CCD arrangement and discharge said first capacitance, said gate means detecting the absence of charge on said first capacitance and the injection of charge from said second capacitance into said second CCD arrangement being blocked, said first and second CCD arrangements comprising charge coupled devices having an input terminal and an output terminal; said first and second capacitances comprising capacitances in the output diffusion zone associated with said output terminal of said first charge coupled device and in the input diffusion zone associated with said input terminal of said second charge coupled device, said means to charge said first capacitance comprising a first transistor connected between said first capacitance and a first control potential terminal, said first transistor having its gate input connected to said first control potential terminal; wherein said means to charge said second capacitance comprises a circuit node, a second transistor connected between said first control potential terminal and said circuit node, said second transistor having its gate input connected to said first control potential terminal and a third transistor connected between said circuit node and said second capacitance, said third transistor having its gate input connected to said circuit node; and comprising additionally a fourth transistor connected between said second capacitance and said first control potential terminal, said fourth transistor having its gate input connected to a second control potential terminal and a third capacitance connected between said first control potential terminal and said second capacitance; the value of said third capacitance being determined in accordance with: ##EQU8## where: C 66 is the capacitance of said third capacitance; C 33 is the capacitance between the input diffusion zone and ground; U R is the amplitude of the voltage pulses in said first control line; U A is the value of the charges stored by the capacitance formed between the output diffusion zone and ground; ΔU A is the value of the charge arriving at said output diffusion zone divided by the output capacitance formed between the output diffusion zone and ground; and δ U is ΔU A divided by 2, which arises when a charge is transmitted to the output diffusion zone.

Claim 31

The combination of two CCD arrangements and a regenerator circuit comprising a first and second CCD arrangement; a first capacitance and means to charge said first capacitance to a predetermined potential; a second capacitance and means to charge said second capacitance to a predetermined potential; means to detect the absence of charge at the output terminal of said first CCD arrangement and not discharging said first capacitance, gate means at the input to said second CCD arrangement detecting the presence of charge on said first capacitance and the injection of charge from said second capacitance into the input terminal of said second CCD arrangement being permitted; means to detect the presence of charge at said output terminal of said first CCD arrangement and discharge said first capacitance, said gate means detecting the absence of charge on said first capacitance and the injection of charge from said second capacitance into said second CCD arrangement being blocked, said first and second CCD arrangements comprising charge coupled devices having an input terminal and an output terminal; said first and second capacitances comprising capacitances in the output diffusion zone associated with said output terminal of said first charge coupled device and in the input diffusion zone associated with said input terminal of said second charge coupled device, said means to charge said first capacitance comprising a first transistor connected between said first capacitance and a first control potential terminal, said first transistor having its gate input connected to said first control potential terminal; wherein said means to charge said second capacitance comprises a circuit node, a second transistor connected between said first control potential terminal and said circuit node, said second transistor having its gate input connected to said first control potential terminal and a third transistor connected between said circuit node and said second capacitance, said third transistor having its gate input connected to said circuit node; and comprising additionally a fourth transistor connected between said second capacitance and said first control potential terminal, said fourth transistor having its gate input connected to a second control potential terminal and a third capacitance connected between said first control potential terminal and said second capacitance; the value of said third capacitance being determined in accordance with: ##EQU8## where: C 66 is the capacitance of said third capacitance; C 33 is the capacitance between the input diffusion zone and ground; U R is the amplitude of the voltage pulses in said first control line; U A is the value of the charges stored by the capacitance formed between the output diffusion zone and ground; ΔU A is the value of the charge arriving at said output diffusion zone divided by the output capacitance formed between the output diffusion zone and ground; and δ U is ΔU A divided by 2, which arises when a charge is transmitted to the output diffusion zone.

Claim 32

The combination of two CCD arrangements and a regenerator circuit comprising a first and second CCD arrangement; A first capacitance and means to charge said first capacitance to a predetermined potential; a second capacitance and means to charge said second capacitance to a predetermined potential; means to direct the absence of charge at the output terminal of said first CCD arrangement and not discharging said first capacitance, gate means at the input to said second CCD arrangement detecting the presence of charge on said first capacitance and the injection of charge from said second capacitance into the input terminal of said second CCD arrangement being permitted; means to detect the presence of charge at said output terminal of said first CCD arrangement and discharge said first capacitance, said gate means detecting the absence of charge on said first capacitance and the injection of charge from said second capacitance into said second CCD arrangement being blocked, said first and second CCD arrangements comprising charge coupled devices having an input terminal and an output terminal; said first and second capacitances comprising capacitances in the output diffusion zone associated with said output terminal of said first charge coupled device and in the input diffusion zone associated with said input terminal of said second charge coupled device, said means to charge said first capacitance comprising a first transistor connected between said first capacitance and a first control potential terminal, said first transistor having its gate input connected to said first control potential terminal; wherein said means to charge said second capacitance comprises a circuit node, a second transistor connected between said first control potential terminal and said circuit node, said second transistor having its gate input connected to said first control potential terminal and a third transistor connected between said circuit node and said second capacitance, said third transistor having its gate input connected to said circuit node; comprising additionally a fourth transistor connected between said second capacitance and a reference potential terminal, said fourth transistor having its gate input connected to a second control potential terminal and a third capacitance connected between said second capacitance and a third control potential terminal; the value of said third capacitance being determined in accordance with: ##EQU9## where: C 75 is the capacitance of said third capacitance; C 33 is the capacitance between the input diffusion zone and ground; U C is the amplitude of the voltage pulses in said third control line; U A is the value of the charges stored by the capacitance formed between the output diffusion zone and ground; ΔU A is the value of the charge arriving at said output diffusion zone divided by the output capacitance formed between the output diffusion zone and ground; and δ U is ΔU A divided by 2, which arises when a charge is transmitted to the output diffusion zone.

Claim 33

The combination of two CCD arrangements and a regenerator circuit comprising a first and second CCD arrangement; A first capacitance and means to charge said first capacitance to a predetermined potential; a second capacitance and means to charge said second capacitance to a predetermined potential; means to direct the absence of charge at the output terminal of said first CCD arrangement and not discharging said first capacitance, gate means at the input to said second CCD arrangement detecting the presence of charge on said first capacitance and the injection of charge from said second capacitance into the input terminal of said second CCD arrangement being permitted; means to detect the presence of charge at said output terminal of said first CCD arrangement and discharge said first capacitance, said gate means detecting the absence of charge on said first capacitance and the injection of charge from said second capacitance into said second CCD arrangement being blocked, said first and second CCD arrangements comprising charge coupled devices having an input terminal and an output terminal; said first and second capacitances comprising capacitances in the output diffusion zone associated with said output terminal of said first charge coupled device and in the input diffusion zone associated with said input terminal of said second charge coupled device, said means to charge said first capacitance comprising a first transistor connected between said first capacitance and a first control potential terminal, said first transistor having its gate input connected to said first control potential terminal; wherein said means to charge said second capacitance comprises a circuit node, a second transistor connected between said first control potential terminal and said circuit node, said second transistor having its gate input connected to said first control potential terminal and a third transistor connected between said circuit node and said second capacitance, said third transistor having its gate input connected to said circuit node; comprising additionally a fourth transistor connected between said second capacitance and a reference potential terminal, said fourth transistor having its gate input connected to a second control potential terminal and a third capacitance connected between said second capacitance and a third control potential terminal; the value of said third capacitance being determined in accordance with: ##EQU9## where: C 75 is the capacitance of said third capacitance; C 33 is the capacitance between the input diffusion zone and ground; U C is the amplitude of the voltage pulses in said third control line; U A is the value of the charges stored by the capacitance formed between the output diffusion zone and ground; ΔU A is the value of the charge arriving at said output diffusion zone divided by the output capacitance formed between the output diffusion zone and ground; and δ U is ΔU A divided by 2, which arises when a charge is transmitted to the output diffusion zone.

Claim 34

The combination of two CCD arrangements and a regenerator circuit comprising a first and second CCD arrangement; a first capacitance and means to charge said first capacitance to a predetermined potential; a second capacitance and means to charge said second capacitance to a predetermined potential; means to detect the absence of charge at the output terminal of said first CCD arrangement and not discharging said first capacitance, gate means at the input to said second CCD arrangement detecting the presence of charge on said first capacitance and the injection of charge from said second capacitance into the input terminal of said second CCD arrangement being permitted; means to detect the presence of charge at said output terminal of said first CCD arrangement and discharge said first capacitance, said gate means detecting the absence of charge on said first capacitance and the injection of charge from said second capacitance into said second CCD arrangement being blocked, said first and second CCD arrangements comprising charge coupled devices having an input terminal and an output terminal; said first and second capacitances comprising capacitances in the output diffusion zone associated with said output terminal of said first charge coupled device and in the input diffusion zone associated with said input terminal of said second charge coupled device, said means to charge said first capacitance comprising a first transistor connected between said first capacitance and a first control potential terminal, said first transistor having its gate connected to said first control potential terminal; wherein said means to charge said second capacitance comprises a circuit node, a second transistor connected between a second control potential terminal and said circuit node, said second transistor having its gate input connected to said second control potential terminal and a third transistor connected between said circuit node and said second capacitance, said third transistor having its gate connected to said circuit node; comprising additionally a fourth transistor connected between said second capacitance and a reference potantial terminal said fourth transistor having its gate input connected to a third control potential terminal.

Claim 35

The combination of two CCD arrangements and a regenerator circuit comprising a first and second CCD arrangement; a first capacitance and means to charge said first capacitance to a predetermined potential; a second capacitance and means to charge said second capacitance to a predetermined potential; means to detect the absence of charge at the output terminal of said first CCD arrangement and not discharging said first capacitance, gate means at the input to said second CCD arrangement detecting the presence of charge on said first capacitance and the injection of charge from said second capacitance into the input terminal of said second CCD arrangement being permitted; means to detect the presence of charge at said output terminal of said first CCD arrangement and discharge said first capacitance, said gate means detecting the absence of charge on said first capacitance and the injection of charge from said second capacitance into said second CCD arrangement being blocked, said first and second CCD arrangements comprising charge coupled devices having an input terminal and an output terminal; said first and second capacitances comprising capacitances in the output diffusion zone associated with said output terminal of said first charge coupled device and in the input diffusion zone associated with said input terminal of said second charge coupled device, said means to charge said first capacitance comprising a first transistor connected between said first capacitance and a first control potential terminal, said first transistor having its gate connected to said first control potential terminal; wherein said means to charge said second capacitance comprises a circuit node, a second transistor connected between a second control potential terminal and said circuit node, said second transistor having its gate input connected to said second control potential terminal and a third transistor connected between said circuit node and said second capacitance, said third transistor having its gate connected to said circuit node; comprising additionally a fourth transistor connected between said second capacitance and a reference potantial terminal said fourth transistor having its gate input connected to a third control potential terminal.

Claim 36

The combination of two CCD arrangement and a regenerator circuit comprising a first and second CCD arrangement; a first capacitance and means to charge said first capacitance to a predetermined potential; a second capacitance and means to charge said second capacitance to a predetermined potential; means to detect the absence of charge at the output terminal of said first CCD arrangement and not discharging said first capacitance, gate means at the input to said second CCD arrangement detecting the presence of charge on said first capacitance and the injection of charge from said second capacitance into the input terminal of said second CCD arrangement being permitted; means to detect the presence of charge at said output terminal of said first CCD arrangement and discharge said first capacitance, said gate means detecting the absence of charge on said first capacitance and the injection of charge from said second capacitance into said second CCD arrangement being blocked, said first and second CCD arrangements comprising charge coupled devices having an input terminal and an output temrinal; said first and second capacitances comprising capacitances in the output diffusion zone associated with said output terminal of said first charge coupled device and in the input diffusion zone associated with said input terminal of said second charge coupled device, said means to charge said first capacitance comprising a first transistor connected between said first capacitance and a first control potential terminal, said first transistor having its gate input connected to a second control potential terminal; wherein said means to charge said second capacitance comprises a second transistor connected between a third control potential terminal and said second capacitance, said second transistor having its gate input connected to said third control potential terminal; comprising additionally a third transistor connected between said second capacitance and a reference potential terminal, said third transistor having its gate input connected to a fourth control potential terminal.

Claim 37

The combination of two CCD arrangement and a regenerator circuit comprising a first and second CCD arrangement; a first capacitance and means to charge said first capacitance to a predetermined potential; a second capacitance and means to charge said second capacitance to a predetermined potential; means to detect the absence of charge at the output terminal of said first CCD arrangement and not discharging said first capacitance, gate means at the input to said second CCD arrangement detecting the presence of charge on said first capacitance and the injection of charge from said second capacitance into the input terminal of said second CCD arrangement being permitted; means to detect the presence of charge at said output terminal of said first CCD arrangement and discharge said first capacitance, said gate means detecting the absence of charge on said first capacitance and the injection of charge from said second capacitance into said second CCD arrangement being blocked, said first and second CCD arrangements comprising charge coupled devices having an input terminal and an output temrinal; said first and second capacitances comprising capacitances in the output diffusion zone associated with said output terminal of said first charge coupled device and in the input diffusion zone associated with said input terminal of said second charge coupled device, said means to charge said first capacitance comprising a first transistor connected between said first capacitance and a first control potential terminal, said first transistor having its gate input connected to a second control potential terminal; wherein said means to charge said second capacitance comprises a second transistor connected between a third control potential terminal and said second capacitance, said second transistor having its gate input connected to said third control potential terminal; comprising additionally a third transistor connected between said second capacitance and a reference potential terminal, said third transistor having its gate input connected to a fourth control potential terminal.