Novel bipolar transistor with a dual-dielectric tunnel emitter

Claim 2

A transistor device having a dual-dielectric tunnel emitter, comprising: a collector region of semiconductor material doped with a p-type doping impurity; a base region of semiconductor material doped with a n-type doping impurity and disposed adjacent to and in physical contact with the collector region to form a n-p, base-collector junction; a first layer of dielectric material of a predetermined thickness having one surface disposed adjacent to and in physical contact with said base region to form a dielectric-semiconductor interface; a second layer of dielectric material of a predetermined thickness having one surface disposed adjacent to and in physical contact with the other surface of said first dielectric layer, said first dielectric layer being sandwiched between said base region and said second dielectric layer to form a dual-dielectric emitter-base junction; means for applying a voltage potential between the other surface of said second dielectric layer and said base region to cause injection of minority carriers across the dielectric-semiconductor interface and into the base region, said minority carrier injection occurring at times when a positive potential of sufficient magnitude is applied to said other dielectric surface of the second layer with respect to said n-type doped base region; and means for applying a voltage potential across the n-p, base-collector junction to transport said injected minority carriers across said n-p, base-collector junction, said base minority carrier transport mechanism occurring when a negative potential of sufficient magnitude is applied to said collector region with respect to said base region.

Claim 3

A transistor device according to claim 1 wherein said first layer is of a thickness to promote a direct tunneling mechanism for injecting minority carriers across the dielectric-semiconductor interface when a positive potential of sufficient magnitude is applied thereacross.

Claim 4

A transistor device according to claim 1 wherein the dielectric material of the first layer is silicon dioxide.

Claim 5

A transistor device according to claim 3 wherein the thickness of the silicon dioxide first layer is less than approximately 30A.

Claim 6

A transistor device according to claim 1 wherein the dielectric material of the second layer is a compound comprising the elements of silicon and nitrogen.

Claim 7

A transistor device according to claim 5 wherein the elements of silicon and nitrogen are substantially equal in proportion.

Claim 8

A transistor device according to claim 5 wherein a range of thickness dimensions for the second layer is 50-500A.

Claim 9

A transistor device having a dual-dielectric tunnel emitter, comprising: a collector region of semiconductor material doped with a n-type doping impurity; a base region of semiconductor material doped with a p-type doping impurity and disposed adjacent to and in physical contact with the collector region to form a p-n, base-collector junction; a first layer of dielectric material of a predetermined thickness having one surface disposed adjacent to and in physical contact with said base region to form a dielectric-semiconductor interface; a second layer of dielectric material of a predetermined thickness having one surface disposed adjacent to and in physical contact with the other surface of said first dielectric layer, said first dielectric layer being sandwiched between said base region and said second dielectric layer to form a dual-dielectric emitter-base junction; means for applying a voltage potential between the other surface of said second dielectric layer and said base region to cause injection of minority carriers across the dielectric-semiconductor interface and into the base region, said minority carrier injection occuring at times when a nagative potential of sufficient magnitude is applied to the other dielectric surface of said second layer with respect to said p-type doped base region; and means for applying a potential across the p-n, base-collector junction to transport said injected minority carriers across said p-n, base-collector junction, said base minority carrier transport mechanism occurring when a positive potential of sufficient magnitude is applied to said collector region with respect to said base region.

Claim 10

A transistor device having a dual-dielectric tunnel emitter, comprising: a collector region of semiconductor material doped with a n-type doping impurity; a base region of semiconductor material doped with a p-type doping impurity and disposed adjacent to and in physical contact with the collector region to form a p-n, base-collector junction; a first layer of dielectric material of a predetermined thickness having one surface disposed adjacent to and in physical contact with said base region to form a dielectric-semiconductor interface; a second layer of dielectric material of a predetermined thickness having one surface disposed adjacent to and in physical contact with the other surface of said first dielectric layer, said first dielectric layer being sandwiched between said base region and said second dielectric layer to form a dual-dielectric emitter-base junction; means for applying a voltage potential between the other surface of said second dielectric layer and said base region to cause injection of minority carriers across the dielectric-semiconductor interface and into the base region, said minority carrier injection occuring at times when a nagative potential of sufficient magnitude is applied to the other dielectric surface of said second layer with respect to said p-type doped base region; and means for applying a potential across the p-n, base-collector junction to transport said injected minority carriers across said p-n, base-collector junction, said base minority carrier transport mechanism occurring when a positive potential of sufficient magnitude is applied to said collector region with respect to said base region.

Claim 11

A transistor device according to claim 8 wherein the first layer is of a thickness to promote a direct tunneling mechanism for injecting minority carriers across the dielectric-semiconductor interface when a negative potential of sufficient magnitude is applied thereacross.

Claim 12

A transistor device according to claim 8 wherein the dielectric material of the first layer is silicon-dioxide.

Claim 13

A transistor device according to claim 10 wherein the thickness of the silicon dioxide first layer is less than approximately 30A.

Claim 14

A transistor device according to claim 8 wherein the dielectric material of the second layer is a compound comprising the elements of silicon and nitrogen.

Claim 15

A transistor device according to claim 12 wherein the elements of silicon and nitrogen are substantially equal in proportion.

Claim 16

A transistor device according to claim 12 wherein a range of thickness dimensions for the second layer is 50-500A.

Claim 17

A transistor circuit for supplying current to a load of predetermined impedance, said circuit comprising: a collector region of semiconductor material doped with a p-type doping impurity; a base region of semiconductor material doped with a n-type doping impurity and disposed adjacent to and in physical contact with the collector region to form a n-p, base-collector junction; a first layer of dielectric material of a predetermined thickness having one surface disposed adjacent to and in physical contact with said base region to form a dielectric-semiconductor interface; a second layer of dielectric material of a predetermined thickness having one surface disposed adjacent to and in physical contact with the other surface of said first dielectric layer, said first dielectric layer being sandwiched between said base region and said second dielectric layer to form a dual-dielectric emitter-base junction; a first means for applying a voltage potential to the other surface of said second dielectric layer; a second means for applying a voltage potential to said base region; a third means for connecting said collector region to said load of predetermined impedance to allow current therebetween; a first source of voltage potential connected to said first means; a second source of voltage potential connected to said second means, said second source having a voltage potential sufficiently negative with respect to said first source such that injection of minority carriers is caused to occur across the dielectric-semiconductor interface and into the base region; and a third source of voltage potential connected to said load of predetermined impedance, said third source having a voltage potential sufficiently negative with respect to said second source to cause a substantial portion of said injected minority carriers to flow across said base-collector junction into said collector region and therefrom through said load, the amount of said minority carrier flow being governed by the voltage differential between said first and second sources.

Claim 18

A transistor circuit for supplying current to a load of predetermined impedance, said circuit comprising: a collector region of semiconductor material doped with a p-type doping impurity; a base region of semiconductor material doped with a n-type doping impurity and disposed adjacent to and in physical contact with the collector region to form a n-p, base-collector junction; a first layer of dielectric material of a predetermined thickness having one surface disposed adjacent to and in physical contact with said base region to form a dielectric-semiconductor interface; a second layer of dielectric material of a predetermined thickness having one surface disposed adjacent to and in physical contact with the other surface of said first dielectric layer, said first dielectric layer being sandwiched between said base region and said second dielectric layer to form a dual-dielectric emitter-base junction; a first means for applying a voltage potential to the other surface of said second dielectric layer; a second means for applying a voltage potential to said base region; a third means for connecting said collector region to said load of predetermined impedance to allow current therebetween; a first source of voltage potential connected to said first means; a second source of voltage potential connected to said second means, said second source having a voltage potential sufficiently negative with respect to said first source such that injection of minority carriers is caused to occur across the dielectric-semiconductor interface and into the base region; and a third source of voltage potential connected to said load of predetermined impedance, said third source having a voltage potential sufficiently negative with respect to said second source to cause a substantial portion of said injected minority carriers to flow across said base-collector junction into said collector region and therefrom through said load, the amount of said minority carrier flow being governed by the voltage differential between said first and second sources.

Claim 19

A transistor circuit according to claim 15 wherein the first layer is of a thickness to promote a direct tunneling mechanism for injecting minority carriers across the dielectric-semiconductor interface when a positive potential of sufficient magnitude being affected by the difference in voltage potentials of the first and second sources is applied thereacross.

Claim 20

A transistor circuit according to claim 15 wherein the dielectric material of the first layer is silicon dioxide.

Claim 21

A transistor circuit according to claim 17 wherein the thickness of the silicon dioxide first layer is less than approximately 30A.

Claim 22

A transistor circuit according to claim 15 wherein the dielectric material of the first layer is aluminum oxide.

Claim 23

A transistor circuit according to claim 15 wherein the dielectric material of the second layer is a compound comprising the elements of silicon and nitrogen.

Claim 24

A transistor circuit according to claim 20 wherein the elements of silicon and nitrogen are substantially equal in proportion.

Claim 25

A transistor circuit according to claim 20 wherein a range of thickness dimensions for the second layer is 50-500A.

Claim 26

A transistor circuit for supplying current to a load of predetermined impedance, said circuit comprising: a collector region of semiconductor material doped with a n-type doping impurity; a base region of semiconductor material doped with a p-type doping impurity and disposed adjacent to and in physical contact with the collector region to form a p-n, base-collector junction; a first layer of dielectric material of a predetermined thickness having one surface disposed adjacent to and in physical contact with said base region to form a dielectric-semiconductor interface; a second layer of dielectric material of a predetermined thickness having one surface disposed adjacent to and in physical contact with the other surface of said first dielectric layer, said first dielectric layer being sandwiched between said base region and said second dielectric layer to form a dual-dielectric emitter-base junction; a first means for applying a voltage potential to the other surface of said second dielectric layer; a second means for applying a voltage potential to said base region; a third means for connecting said collector region to said load of predetermined impedance to allow current therebetween; a first source of voltage potential connected to said first means; a second source of voltage potential connected to said second means, said second source having a voltage potential sufficiently positive with respect to said first source such that injection of minority carriers is caused to occur across the dielectric-semiconductor interface and into the base region; and a third source of voltage potential connected to said load of predetermined impedance, said third source having a voltage potential sufficiently positive with respect to said second source to cause a substantial portion of said injected minority carriers to flow across said base-collector junction into said collector region and therefrom through said load, the amount of said load current being governed by the voltage differential between said first and second sources.

Claim 27

A transistor circuit for supplying current to a load of predetermined impedance, said circuit comprising: a collector region of semiconductor material doped with a n-type doping impurity; a base region of semiconductor material doped with a p-type doping impurity and disposed adjacent to and in physical contact with the collector region to form a p-n, base-collector junction; a first layer of dielectric material of a predetermined thickness having one surface disposed adjacent to and in physical contact with said base region to form a dielectric-semiconductor interface; a second layer of dielectric material of a predetermined thickness having one surface disposed adjacent to and in physical contact with the other surface of said first dielectric layer, said first dielectric layer being sandwiched between said base region and said second dielectric layer to form a dual-dielectric emitter-base junction; a first means for applying a voltage potential to the other surface of said second dielectric layer; a second means for applying a voltage potential to said base region; a third means for connecting said collector region to said load of predetermined impedance to allow current therebetween; a first source of voltage potential connected to said first means; a second source of voltage potential connected to said second means, said second source having a voltage potential sufficiently positive with respect to said first source such that injection of minority carriers is caused to occur across the dielectric-semiconductor interface and into the base region; and a third source of voltage potential connected to said load of predetermined impedance, said third source having a voltage potential sufficiently positive with respect to said second source to cause a substantial portion of said injected minority carriers to flow across said base-collector junction into said collector region and therefrom through said load, the amount of said load current being governed by the voltage differential between said first and second sources.

Claim 28

A transistor circuit according to claim 23 wherein the first layer is of a thickness to promote a direct tunneling mechanism for injecting minority carriers across the dielectric-semiconductor interface when a negative potential of sufficient magnitude being affected by the difference in voltage potentials of the first and second sources is applied thereacross.

Claim 29

A transistor circuit according to claim 23 wherein the dielectric material of the first layer is silicon-dioxide.

Claim 30

A transistor circuit according to claim 23 wherein the dielectric material of the first layer is aluminum oxide.

Claim 31

A transistor circuit according to claim 10 wherein the thickness of the silicon dioxide first layer is less than approximately 30A.

Claim 32

A transistor circuit according to claim 8 wherein the dielectric material of the second layer is a compound comprising the elements of silicon and nitrogen.

Claim 33

A transistor circuit according to claim 12 wherein the elements of silicon and nitrogen are substantially equal in proportion.

Claim 34

A transistor circuit according to claim 12 wherein a range of thickness dimensions for the second layer is 50-500A.