US4136356A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Wiring substrate for a matrix circuit
Assignee: Hitachi Ltd
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Filing: 1977-08-12
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Granted: 1979-01-23
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Expires: 1997-08-12
Abstract
Abstract A wiring substrate for a matrix circuit constituted by mounting a plurality of semiconductor chips in a multi-chip configuration, in which wiring conductors for interconnecting terminal electrodes of the individual chips and terminals of incoming and outgoing lines of the matrix circuit consist of first wiring conductors each for interconnecting the terminal electrodes of adjacent two chips and second wiring conductors for interconnecting the first wiring conductors at their middle portions, whereby the wiring lengths of the wiring conductors through any chips are made substantially equal to one another, thereby to establish uniform resistance among the wiring conductors for the chips with the width of the wiring conductors maintained constant.
Inventors
- 👤 Masaaki Kusano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 00:26
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/611; H10W70/62; H10W70/65; H10W90/00
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
88 words
A wiring substrate for a matrix circuit including a plurality of semiconductor chips having incoming and outgoing electrodes in multi-chip configuration and incoming and outgoing lines to be connected to the electrodes of said semiconductor chips, comprising: incoming and outgoing line multi-wiring conductors for interconnecting the electrodes of said semiconductor chips associated with the same incoming and outgoing lines; incoming and outgoing line terminal electrodes; and conductor means for connecting said terminal electrodes with the middle portions intermediate the ends of the associated ones of said multi-wiring conductors.
Claim 2
Dependent Claim
88 words
A wiring substrate for a matrix circuit including a plurality of semiconductor chips having incoming and outgoing electrodes in multi-chip configuration and incoming and outgoing lines to be connected to the electrodes of said semiconductor chips, comprising: incoming and outgoing line multi-wiring conductors for interconnecting the electrodes of said semiconductor chips associated with the same incoming and outgoing lines; incoming and outgoing line terminal electrodes; and conductor means for connecting said terminal electrodes with the middle portions intermediate the ends of the associated ones of said multi-wiring conductors.
Claim 3
Dependent Claim
76 words
A wiring substrate as set forth in claim 1, in which among said multi-wiring conductors at least incoming line multi-wiring conductors include first wiring conductors each for connecting the electrodes of two adjacent chips associated with a respective incoming line and second wiring conductors each for interconnecting the middle portions intermediate the ends of two adjacent first wiring conductors, the middle portion intermediate the ends of said second wiring conductors being connected to said conductor means.
Claim 4
Dependent Claim
40 words
A wiring substrate for a matrix circuit as set forth in claim 2, wherein said first wiring conductors and said second wiring conductors are provided separately in upper and lower layers, respectively, for wiring incoming lines of said matrix circuit.
Claim 5
Dependent Claim
55 words
A wiring substrate for a matrix circuit as set forth in claim 2, wherein said first and second wiring conductors are separately provided in two layers at least partly superposed through an insulation layer and connected to one another by through-hole connection, whereby said first and second wiring conductors are located on superposed straight lines.
Claim 6
Dependent Claim
76 words
A wiring substrate as set forth in claim 1, in which among said multi-wiring conductors at least outgoing line multi-wiring conductors include first wiring conductors each for connecting the electrodes of two adjacent chips associated with a respective outgoing line and second wiring conductors each for interconnecting the middle portions intermediate the ends of two adjacent first wiring conductors, the middle portion intermediate the ends of said second wiring conductors being connected to said conductor means.
Claim 7
Dependent Claim
40 words
A wiring substrate for a matrix circuit as set forth in claim 5, wherein said first wiring conductors and said second wiring conductors are provided separately in upper and lower layers, respectively, for wiring outgoing lines of said matrix circuit.
Claim 8
Dependent Claim
55 words
A wiring substrate for a matrix circuit as set forth in claim 5, wherein said first and second wiring conductors are separately provided in two layers at least partly superposed through an insulation layer and connected to one another by through-hole connection, whereby said first and second wiring conductors are located on superposed straight lines.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-01-22 | 1982-07-24 | 1983-01-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-01-22 | 1986-07-24 | 1987-01-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-01-22 | 1990-07-24 | 1991-01-23 | $7700.00 | Window Closed / Lapsed |