Series read only memory structure

Claim 2

A logic structure comprising: A semiconductor substrate having a plurality of groups of field affect transistors formed at selected locations thereon, each of said transistors having portions defining a gate, a source, and a drain; each group of transistors being arrayed in a set of input rows and a set of output columns; the gates of the transistors in each output row being formed in common; the drains of transistors within each output column being connected in series electrical relation to the sources of adjacent transistors in each output column, whereby a gate controlled, series conduction path is established through each output column of transistors in each group; means for electrically connecting each corresponding input row of each group to form common input lines; and, means for selectively coupling corresponding output columns of each group to a common output line, said coupling means being responsive to a bias potential which corresponds to a selected logic state to electrically connect or disconnect its associated output column to or from the common output line.

Claim 3

The logic structure as defined in claim 1, wherein each transistor of each group is of a first or second type, the transistors of said first and second types including structurally differentiating portions which provide first and second modes of operation, respectively, each transistor of said first type being operable in said first mode to conduct current through its source and drain portions in response to an applied gate potential corresponding to a first logic state, and being operable to prevent the flow of current through its source and drain portions in response to an applied gate potential corresponding to a second logic state, whereby a gate controlled series conduction path is established in the output columns containing the transistors of said first type; each transistor of said second type being operable in said second mode to conduct current through its source and drain portions independently of the logic state corresponding to its applied gate potential, whereby a series conduction path is established in each output column containing a transistor of said second type which is logically unresponsive to changes in the logic state corresponding to an applied gate potential.

Claim 4

The combination as defined in claim 2, at least a portion of the channel region of each transistor of said first type having ions implanted therein in a first concentration level of sufficient magnitude to permit operation of each transistor of said first type in said first mode, and at least a portion of the channel region of each transistor of said second type having ions implanted therein in a second concentration level of sufficient magnitude to permit operation of each transistor of said second type in said second mode.

Claim 5

The combination as defined in claim 3, wherein the ion impurities implanted in the channel region of each transistor of said first type are of a first conductivity type, and the ion impurities implanted in the channel region of each transistor of said second type are of the opposite conductivity type.

Claim 6

The combination as defined in claim 2, at least a portion of the channel region of each transistor of said first type having ion impurities implanted therein in a concentration level of sufficient magnitude to permit operation thereof in said first mode, the channel region of each transistor of the second type being devoid of ion impurities to permit operation thereof in said second mode.

Claim 7

The combination as defined in claim 2, the channel of each transistor of said first type being devoid of ion impurities to permit operation thereof in said first mode and at least a portion of the channel region of each transistor of said second type having ion impurities implanted thereof in a concentration level of sufficient magnitude to permit operation thereof in said second mode.

Claim 8

The combination as defined in claim 2, the drains and sources of adjacent transistors in each output column being formed by a common elongated diffused region within said substrate, the common elongated diffused regions of adjacent output columns extending substantially parallel to each other and defining a continuous channel region therebetween, the gates of the transistors in each input row being formed by a common conductive gate strip extending transversely with respect to the source and drain diffusion regions, and a layer of insulating material being disposed under the gate strips and over the channel regions defined by the adjacent source and drain regions.

Claim 9

The combination as defined in claim 7, said common conductive gate strip comprising a layer of polycrystalline silicon overlaying said channel region.

Claim 10

The combination as defined in claim 7, said common gate strip comprising a conductive metalized layer disposed on said layer of insulating material.

Claim 11

The combination as defined in claim 7, said insulating layer being sufficiently thin to establish transistors operable in said first mode at the intersection of each gate strip and the associated source and drain regions at the matrix locations corresponding to each transistor of said first type, and including a conductive bridge region electrically interconnecting the source and drain portions of each transistor of said second type.