US4146931A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital filter
Assignee: Alcatel Lucent NV
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Filing: 1978-02-10
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Granted: 1979-03-27
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Expires: 1998-02-10
Abstract
Abstract A digital filter configuration incorporating read-only memories for coefficient storage is disclosed in which substantial reduction in memory requirements is achieved. Two read-only memories are addressed by only three arguments for a second-order filter or five arguments for a fourth-order filter.
Inventors
- 👤 Jean-Marie Delforge
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 14:53
CPC Classifications
H; H03; H03H; H03H17/00; H03H17/02; H03H17/04; H03H17/0405
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
287 words
A digital filter for filtering successive binary coded input samples X(n) in the form: ##EQU13## in which n is the number of the sample, B is the number of bits, per sample, and furnishing a series of coded values Y(n) related to the said input samples by the relationship: ##EQU14## in which m is the order of the filter, αi and βi are weighting factors, comprising: first memory means furnishing a first value φ j (Y) from m+1 address bits; second memory means furnishing a second value φ j (W) from the same m+1 address bits; first means to combine the said successive first values φ j (Y) so as to obtain a final value: ##EQU15## second means to combine the said successive second value φ j (W) so as to obtain an intermediate value: ##EQU16## third means to apply serially to the said first and second memory means the B bits of the said input sample X(n); fourth means to apply serially to the said first and second memory means the B bits of each of the said intermediate values W(n-1) to W(n-m), the m j th bits of the said intermediate values constituting with the j th bit of the said input sample the m+1 address bits of the said memories; and in that the said first value φ j (Y) is related to the said m+1 address bits by the relationship: φ.sub.j (Y) = X.sub.i (n) + (α.sub.1 -β.sub.1).W.sub.j (n-1) + (α.sub.2 -β.sub.2).W.sub.j (n-2) . . . + (αm-βm).W.sub.j (n-m) and the second value φ j (W) is related to the said m+1 address bits by the relationship: φ.sub.j (W) = X.sub.j (n) - β.sub.1.W.sub.j (n-1) - β.sub.2.W.sub.j (n-2) . . . -βm.W.sub.j (n-m).
Claim 2
Dependent Claim
287 words
A digital filter for filtering successive binary coded input samples X(n) in the form: ##EQU13## in which n is the number of the sample, B is the number of bits, per sample, and furnishing a series of coded values Y(n) related to the said input samples by the relationship: ##EQU14## in which m is the order of the filter, αi and βi are weighting factors, comprising: first memory means furnishing a first value φ j (Y) from m+1 address bits; second memory means furnishing a second value φ j (W) from the same m+1 address bits; first means to combine the said successive first values φ j (Y) so as to obtain a final value: ##EQU15## second means to combine the said successive second value φ j (W) so as to obtain an intermediate value: ##EQU16## third means to apply serially to the said first and second memory means the B bits of the said input sample X(n); fourth means to apply serially to the said first and second memory means the B bits of each of the said intermediate values W(n-1) to W(n-m), the m j th bits of the said intermediate values constituting with the j th bit of the said input sample the m+1 address bits of the said memories; and in that the said first value φ j (Y) is related to the said m+1 address bits by the relationship: φ.sub.j (Y) = X.sub.i (n) + (α.sub.1 -β.sub.1).W.sub.j (n-1) + (α.sub.2 -β.sub.2).W.sub.j (n-2) . . . + (αm-βm).W.sub.j (n-m) and the second value φ j (W) is related to the said m+1 address bits by the relationship: φ.sub.j (W) = X.sub.j (n) - β.sub.1.W.sub.j (n-1) - β.sub.2.W.sub.j (n-2) . . . -βm.W.sub.j (n-m).
Claim 3
Dependent Claim
79 words
A digital filter according to claim 1, wherein said first means and the said second means include: adder-subtractor means receiving at one input thereof said first value or said second value; register means having an input which is connected to the output of said adder-subtractor means; and a divide-by-two divider circuit having an input which is connected to the output of said register means and having an output which is connected to a second input of said adder-subtractor means.
Claim 4
Dependent Claim
35 words
A digital filter according to claim 1 wherein said first and second values are applied to the said first means which are then used in multiplexed operation by the said first and second memory means.
Claim 5
Dependent Claim
26 words
A digital filter according to claim 1 wherein said third means comprises parallel-serial register means receiving in parallel the B bits of the input sample X(n).
Claim 6
Dependent Claim
47 words
A digital filter according to claim 1 wherein said fourth means comprises m shift registers of B bits arranged serially, the first of said shift registers receiving the said intermediate value W(n) and the outputs of said shift registers representing the intermediate values W(n-1) to W(n-m) respectively.
References Cited (Backward Citations)
US3772659A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-03-26 | 1982-09-25 | 1983-03-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-03-26 | 1986-09-25 | 1987-03-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-03-26 | 1990-09-25 | 1991-03-27 | $7700.00 | Window Closed / Lapsed |