Superconducting memory array configurations which avoid spurious half-select condition in unselected cells of the array

Abstract

Abstract A number of memory array configurations which avoid a spurious half-select condition in unselected cells of a superconducting memory array is disclosed. The memory arrays incorporate memory cells which include at least single Josephson junction disposed in a superconducting loop wherein binary information is stored in the form of at least one circulating current. By providing means for applying a control magnetic field to only the selected memory cell, spurious writing of an unselected memory cell is avoided. This is accomplished in a number of embodiments by causing the application of the half-select current (which normally provides the control magnetic field to a memory cell) to divert a previously applied half-select or enabling current to the memory cell into another path so that the previously applied half-select or enabling current now acts as a control current for switching the storage gate of the selected memory cell. Diverson of the enabling current is, in turn, achieved by the switching of a serially disposed Josephson device which switches in response to the presence of two half-select currents in that device. Any othersimilarly serially disposed device in an unselected memory cell encounters only a single half-select current and, under such circumstances, cannot switch to control its associated storage gate. Any other unselected cell encounters, at most, a single half-select current.

Inventors

• 👤 Sadeg M. Faris

Bibliographic Details