US4159527A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Wave generator
Assignee: Toshiba Corp
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Filing: 1978-01-19
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Granted: 1979-06-26
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Expires: 1998-01-19
Abstract
Abstract A periodic function wave generator is provided in a digital phase synchronizing circuit which comprises a memory circuit for storing the values of n phases obtained by equally dividing one period of a sine wave by 4n and each having a phase θ=90°/n(i+0.5), where n represents an integer and i is an integer of from 0 to n-1, a circuit for designating a predetermined one of these phases in one period, a circuit for converting an address read out of the memory circuit into one of the n phases in accordance with one of the ranges of 0° to 90°, 90° to 180°, 180° to 270° and 270° to 360° and a circuit for inverting the sign of the output of the memory circuit in accordance with the particular range in which the designated phase falls.
Inventors
- 👤 Haruki Yahata
- 👤 Shunsuke Honda
- 👤 Tadamichi Kawasaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 01:37
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/32; H04L27/34; H04L27/38; H04L27/3818; G; G06; G06F; G06F1/00; G06F1/02; G06F1/03; G06F1/035; G06F1/0353; H04L27/02; H04L27/06; H04L27/066
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
164 words
A periodic function wave generator comprising means for designating a predetermined phase in one period of a periodic function signal, a circuit for producing a periodic function value of said designated phase, means for utilizing the output of said producing circuit to control said phase designating means, a memory circuit for storing the values of n phases of a periodic function obtained by equally dividing one period of said periodic function by 4N, each of said N values having a phase θ=90°/n (i+0.5), where n represents an integer, and i represents an integer of 0 to n-1, circuit means for converting the value of an address read out of said memory circuit into one of said n phases in accordance with one of the ranges of 0°-90°, 90°-180°, 180°-270°, and 270°-360° in which said designated phase falls, and a circuit for inverting the sign of the output of said producing circuit in accordance with one of said ranges in which said designated phase falls.
Claim 2
Dependent Claim
164 words
A periodic function wave generator comprising means for designating a predetermined phase in one period of a periodic function signal, a circuit for producing a periodic function value of said designated phase, means for utilizing the output of said producing circuit to control said phase designating means, a memory circuit for storing the values of n phases of a periodic function obtained by equally dividing one period of said periodic function by 4N, each of said N values having a phase θ=90°/n (i+0.5), where n represents an integer, and i represents an integer of 0 to n-1, circuit means for converting the value of an address read out of said memory circuit into one of said n phases in accordance with one of the ranges of 0°-90°, 90°-180°, 180°-270°, and 270°-360° in which said designated phase falls, and a circuit for inverting the sign of the output of said producing circuit in accordance with one of said ranges in which said designated phase falls.
Claim 3
Dependent Claim
178 words
A digital phase synchronizing circuit comprising means for designating a predetermined phase in one period of a periodic function signal, a circuit for producing a periodic function value of said designated phase, a multiplying circuit for multiplying said periodic function value with an input from outside, means for utilizing the output of said multiplying circuit to control said phase designating means, a memory circuit for storing the values of n phases of a periodic function obtained by equally dividing one period of said periodic function by 4n, each of said N values having a phase θ=90°/n (i+0.5), where n represents an integer, and i represents an integer of 0 to n-1, circuit means for converting the value of an address read out of said memory circuit into one of said n phases in accordance with one of the ranges of 0°-90°, 90°-180°, 180°-270°, and 270°-360° in which said designated phase falls, and a circuit for inverting the sign of the output of said multiplying circuit in accordance with one of said ranges in which said designated phase falls.
Claim 4
Dependent Claim
178 words
A digital phase synchronizing circuit comprising means for designating a predetermined phase in one period of a periodic function signal, a circuit for producing a periodic function value of said designated phase, a multiplying circuit for multiplying said periodic function value with an input from outside, means for utilizing the output of said multiplying circuit to control said phase designating means, a memory circuit for storing the values of n phases of a periodic function obtained by equally dividing one period of said periodic function by 4n, each of said N values having a phase θ=90°/n (i+0.5), where n represents an integer, and i represents an integer of 0 to n-1, circuit means for converting the value of an address read out of said memory circuit into one of said n phases in accordance with one of the ranges of 0°-90°, 90°-180°, 180°-270°, and 270°-360° in which said designated phase falls, and a circuit for inverting the sign of the output of said multiplying circuit in accordance with one of said ranges in which said designated phase falls.
Claim 5
Dependent Claim
33 words
The digital phase synchronizing circuit according to claim 2 wherein said memory circuit comprises a read only memory circuit and said sign inverting circuit is connected to the output of said multiplying circuit.
Claim 6
Dependent Claim
36 words
The digital phase synchronizing circuit according to claim 2 wherein said memory circuit comprises a read only memory circuit and said sign inverting circuit is connected between said multiplying circuit and said read only memory circuit.
Claim 7
Dependent Claim
30 words
The digital phase synchronizing circuit according to claim 2 which further comprises means for storing predetermined phase values for a 1/4 period of said periodic function in said memory circuit.
Claim 8
Dependent Claim
30 words
The digital phase synchronizing circuit according to claim 2 which further comprises means for storing predetermined phase values for a 1/2 period of said periodic function in said memory circuit.
Claim 9
Dependent Claim
18 words
The digital phase synchronizing circuit according to claim 2 wherein said phase synchronizing circuit comprises a Costas loop.
Claim 10
Dependent Claim
62 words
The digital phase synchronizing circuit according to claim 2 wherein the contents stored in said memory circuits are said N values wherein each of said N values has been multiplied by a constant which is approximately equal to one, the value of said constant selected such that each bit of the maximum value stored in said memory circuit is a logic "one".
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-06-25 | 1982-12-25 | 1983-06-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-06-25 | 1986-12-25 | 1987-06-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-06-25 | 1990-12-25 | 1991-06-26 | $7700.00 | Window Closed / Lapsed |