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US4169256A Expired / Lapsed US ⏱️ 0.0 years remaining

Digitally controlled oscillator

Assignee: Thales Nederland BV
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Filing: 1977-08-17
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Granted: 1979-09-25
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Expires: 1997-08-17
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Abstract

Abstract A digitally controlled oscillator is provided with a memory, storing the half periods T i (i=1, 2, ..., n) of corresponding frequencies f i =1/(2T i ) to be generated, and with a digital feedback circuit, in which circuit the half periods taken from memory are decreased by a fixed time value τ on a time sharing basis, and in which circuit, as soon as the residual values Δ i ,1 =T i -k i ,1 τ<τ are obtained, these residual values are increased by the corresponding half periods T i also on a time sharing basis, and each value so increased is repeatedly decreased by the fixed time τ. On repeating this process j times, the residual values can be expressed by: Δ i ,j =T i +Δ i ,j-1 -k i ,j τ, where each k i ,j is so large that 0≦Δ i ,j <τ. The digital feedback circuit is connected to n residual value counters, which are each supplied with a series of residual values Δ i ,j and which, on reaching a fixed value, bring about that a circuit connected to the respective counter produces a square-wave signal of frequency f i .

Inventors

  • 👤 Jan Bergman
  • 👤 Klaas J. Luidens

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-01 19:11
CPC Classifications
G; G01; G01S; G01S15/00; G01S15/02; G01S15/50; Y; Y10; Y10S; Y10S367/00; Y10S367/904

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 255 words
A digitally controlled oscillator for use in a sonar transmitter/receiver comprising: a memory, storing the half periods T i (i=1,2,...,n) of corresponding frequencies f i =1/(2T i ) to be generated; a digital feedback circuit connected to said memory; said circuit decreasing each of the half periods taken from memory after a fixed time interval τby the value τon a time sharing basis; n counters to count residual values; said digital feedback circuit connected to said n residual value counters, each counter being supplied with a series of residual values Δ i ,j ; in which circuit as soon as the residual values Δ i ,1 i,=T i -k i ,1 <τ, where k i ,1 is an integer are obtained, said residual values are increased by the corresponding half periods T i also on a time sharing basis, and each value so increased is repeatedly decreased after a fixed time interval τ by the value τ whereby after the process of increasing by T i and repeatedly decreasing by τ has been performed j times the residual values can be expressed by: Δ i ,j =T i +Δ i ,j-1 -k i ,j τ, where each k i ,j is so large that 0≦Δ i ,j <τ; a conversion circuit; said counters on reaching a fixed value after writing of a residual value from the respective series, delivering a signal to said conversion circuit connected to the respective counter, which circuit converts the applied signals into a square-wave signal of frequency f i .
Claim 2
Dependent Claim 255 words
A digitally controlled oscillator for use in a sonar transmitter/receiver comprising: a memory, storing the half periods T i (i=1,2,...,n) of corresponding frequencies f i =1/(2T i ) to be generated; a digital feedback circuit connected to said memory; said circuit decreasing each of the half periods taken from memory after a fixed time interval τby the value τon a time sharing basis; n counters to count residual values; said digital feedback circuit connected to said n residual value counters, each counter being supplied with a series of residual values Δ i ,j ; in which circuit as soon as the residual values Δ i ,1 i,=T i -k i ,1 <τ, where k i ,1 is an integer are obtained, said residual values are increased by the corresponding half periods T i also on a time sharing basis, and each value so increased is repeatedly decreased after a fixed time interval τ by the value τ whereby after the process of increasing by T i and repeatedly decreasing by τ has been performed j times the residual values can be expressed by: Δ i ,j =T i +Δ i ,j-1 -k i ,j τ, where each k i ,j is so large that 0≦Δ i ,j <τ; a conversion circuit; said counters on reaching a fixed value after writing of a residual value from the respective series, delivering a signal to said conversion circuit connected to the respective counter, which circuit converts the applied signals into a square-wave signal of frequency f i .
Claim 3
Dependent Claim 123 words
A digitally controlled oscillator as claimed in claim 1, wherein said digital feedback circuit comprises: an adding circuit, in which the residual values Δ i ,j- 1 < τ are increased by the corresponding value of the half periods T i ; and a subtracting circuit connected to said adding circuit, in which subtracting circuit after a fixed time interval τ the applied values are decreased by the value t and are subsequently stored in said working memory connected to said subtracting circuit, from which memory the stored values are fed back to said subtracting circuit via said adding circuit until the obtained residual values Δ i ,j <τ, whereupon said residual values are again increased by T i in said adding circuit.
Claim 4
Dependent Claim 67 words
A digitally controlled oscillator as claimed in claim 2, further including: a control unit which in response to the time values stored in said working memory, effectuates that the residual values Δ i ,j- 1 applied to the adding circuit are increased by the corresponding half periods T i as soon as the condition Δ i ,j- 1 <τ, where i=1, 2, ..., n has been satisfied.
Claim 5
Dependent Claim 37 words
A digitally controlled oscillator as claimed in claim 3, wherein said control unit delivers the signals by which the residual values Δ i ,j <τ from said working memory are fed to the corresponding residual value counters.
Claim 6
Dependent Claim 173 words
A digitally controlled oscillator as claimed in claim 4 further including: a sonar transmitter/receiver comprising: m radially directed receiver channels for receiving sonar signals of frequency f o .sbsb.i =F z +f d .sbsb.i +F ed .sbsb.i, where i=1, 2, ..., m; F z is the transmitting frequency of the sonar transmitter, F d .sbsb.i is the doppler frequency of a target detected in receiver channel i, and F ed .sbsb.i is the doppler frequency in receiver channel i due to the motion of the sonar transmitter/receiver; a mixer for each receiver channel; whereby each of the m receiver channels is provided with a mixer for transposing the sonar signals of frequency f o .sbsb.i to those of frequency f d .sbsb.i, wherein the signals of mixing frequency f z +f ed .sbsb.i for the m receiver channels are produced by said digitally controlled oscillator; a computer; said computer determining the half periods T i = 1/[2(f z +F ed .sbsb.i)], where i=1,2,...,n, which half periods are applied to said digitally controlled oscillator.
Claim 7
Dependent Claim 40 words
A digitally controlled oscillator as claimed in claim 5, wherein the number of frequencies (n) to be generated in said digitally controlled oscillator is smaller than or equal to the number of said recever channels (m) of said sonar transmitter/receiver.

References Cited (Backward Citations)

US3370266A Cited
US3810038A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1982-09-24 1983-03-26 1983-09-25 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1986-09-24 1987-03-26 1987-09-25 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1990-09-24 1991-03-26 1991-09-25 $7700.00 Window Closed / Lapsed

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