US4179731A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Microprogrammed control system
Assignee: Toshiba Corp
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Filing: 1977-04-04
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Granted: 1979-12-18
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Expires: 1997-04-04
Abstract
Abstract A microprogrammed control system comprises: a memory for storing a microprogram programmed with microinstructions; a memory for storing microinstructions for branching microinstruction; an address register for storing the address of the microinstruction to be next executed; and a microinstruction register for storing the microinstruction to be executed. The program operation of the microprogrammed control system depends on whether the micro-instruction stored in the microinstruction register is the branching one or not. In the case of non-branching microinstruction, the operation of ordinary microinstructions is executed. In the case of branching microinstruction, a special operation is executed for making the operation of the branching microinstruction equivalent to that of the ordinary microinstruction.
Inventors
- 👤 Isamu Yamazaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 23:46
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/26; G06F9/262; G06F9/264; G06F9/267
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
284 words
A microprogrammed control system comprising: a first memory for storing a microprogram having ordinary and branch instructions, the branch instruction including an operation code, a control code and an address, said first memory including an address input port; a second memory for storing instructions, which includes an address input port; an address register for storing an address of an instruction to be next executed, which includes an input port; address updating means for updating the address in the address register to a further next instruction; an instruction register for storing a currently executed instruction, which includes an input port; first means connected to the instruction register for generating a first signal when the instruction in the instruction register is the ordinary instruction and a second signal when the instruction is the branch instruction; second means connected to the first means and responsive to the first signal for transferring the instruction to be next executed which corresponds to the address in the address register from the first memory to the input port of the instruction register and for transferring the update address of the address updating means to the address input port of the address register; and third means connected to the first means and responsive to the second signal for transferring the branch address designated by the branch instruction into the address input port of the address register and for transferring an instruction designated by the control code of the branch instruction in the instruction register from the second memory to the input port of the instruction register, said branch address and said instruction from the second memory being stored in the address register and the instruction register in response to a clock pulse.
Claim 2
Dependent Claim
284 words
A microprogrammed control system comprising: a first memory for storing a microprogram having ordinary and branch instructions, the branch instruction including an operation code, a control code and an address, said first memory including an address input port; a second memory for storing instructions, which includes an address input port; an address register for storing an address of an instruction to be next executed, which includes an input port; address updating means for updating the address in the address register to a further next instruction; an instruction register for storing a currently executed instruction, which includes an input port; first means connected to the instruction register for generating a first signal when the instruction in the instruction register is the ordinary instruction and a second signal when the instruction is the branch instruction; second means connected to the first means and responsive to the first signal for transferring the instruction to be next executed which corresponds to the address in the address register from the first memory to the input port of the instruction register and for transferring the update address of the address updating means to the address input port of the address register; and third means connected to the first means and responsive to the second signal for transferring the branch address designated by the branch instruction into the address input port of the address register and for transferring an instruction designated by the control code of the branch instruction in the instruction register from the second memory to the input port of the instruction register, said branch address and said instruction from the second memory being stored in the address register and the instruction register in response to a clock pulse.
Claim 3
Dependent Claim
45 words
A microprogrammed control system according to claim 1 wherein the first means comprises a decoder connected to the instruction register for generating the first signal in response to the ordinary instruction in the instruction register or the second signal in response to the branch instruction.
Claim 4
Dependent Claim
170 words
A microprogrammed control system according to claim 1 wherein the second means comprises a first gate circuit connected between the first memory and the instruction register for transferring the instruction from the first memory to the input port of the instruction register in response to the first signal from the first means, and a second gate circuit connected between the address updating means and the address register for transferring an update address from the address updating means into the input port of the address register; and the third means comprises a third gate circuit connected between the second memory and the instruction register for transferring an instruction from the second memory into the instruction register in response to the second signal from the first means and a fourth gate circuit connected between the instruction register and the address register for transferring the branch address of the branch instruction in the instruction register to the input port of the address register in response to the second signal from the first means.
Claim 5
Dependent Claim
33 words
A microprogrammed control system according to claim 1 wherein the address updating means comprises an adder for adding an integer to the address transferred from the address register to produce an update address.
Claim 6
Dependent Claim
178 words
A microprogrammed control system according to claim 1 wherein the second means comprises a first gate circuit connected between the first memory and the instruction register for leading the instruction from the first memory to the input port of the instruction register in response to the first signal from the first means, and a second gate circuit connected between the address updating means and the address register for leading an update address from the address updating means into the input port of the address register; and the third means comprises a third gate circuit connected between the second memory and the instruction register for leading an instruction from the second memory into the input port of the instruction register in response to the second signal from the first means and a fourth gate circuit connected between the instruction register and the address register for leading the address designated by the branch instruction in the instruction register from the instruction register to the input port of the address register in response to the second signal from the first means.
Claim 7
Dependent Claim
34 words
A microprogrammed control system according to claim 5 wherein the address updating means comprises an adder for adding an integer to the address transferred from the address register therein to produce an update address.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-12-17 | 1983-06-18 | 1983-12-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-12-17 | 1987-06-18 | 1987-12-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-12-17 | 1991-06-18 | 1991-12-18 | $7700.00 | Window Closed / Lapsed |