US4179747A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Mailing system
Assignee: Pitney Bowes Inc
•
Filing: 1978-07-24
•
Granted: 1979-12-18
•
Expires: 1998-07-24
Abstract
Abstract A system for mailing articles includes an integrated circuit interface between a scale deflection transducer, a processor and an external memory. The interface includes a multifunction shift register array which is adapted to receive count data indicative of the weight of an article. Communication between the shift register array, the processor and the memory is such that the shift registers are selectively utilized for memory address and data transfer without the necessity of clearing prior operands.
Inventors
- 👤 Daniel F. Dlugos
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 12:56
CPC Classifications
G; G01; G01G; G01G19/00; G01G19/002; G01G19/005; G01G19/40; G01G19/413
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
111 words
An interface for providing selective information transfer channels between a processing unit, a memory and a peripheral, the interface comprising register means for storing and transferring information, the register means including means for receiving information in a parallel mode and means for transferring information in a parallel mode, the parallel mode transfer means being adapted to address the memory and the parallel receiving means being adapted to load memory information into the register means, the processing unit including means for simultaneous serial loading of address information into the register means and serial unloading of memory information from the register means, the register means being thereby adapted to effect reduced cycle time.
Claim 2
Dependent Claim
111 words
An interface for providing selective information transfer channels between a processing unit, a memory and a peripheral, the interface comprising register means for storing and transferring information, the register means including means for receiving information in a parallel mode and means for transferring information in a parallel mode, the parallel mode transfer means being adapted to address the memory and the parallel receiving means being adapted to load memory information into the register means, the processing unit including means for simultaneous serial loading of address information into the register means and serial unloading of memory information from the register means, the register means being thereby adapted to effect reduced cycle time.
Claim 3
Dependent Claim
50 words
An interface for providing selective information transfer channels between a processing unit, a memory and a peripheral device constructed in accordance with claim 1 wherein the parallel load receiving means further includes means adapted to selectively parallel load either the memory information or peripheral device information into the register means.
Claim 4
Dependent Claim
16 words
An interface constructed in accordance with claim 2 wherein the selective loading means comprises multiplexing means.
References Cited (Backward Citations)
US3535694A
Cited
US3587059A
Cited
US3638195A
Cited
US3675215A
Cited
US3713096A
Cited
US3868643A
Cited
US3969704A
Cited
US3967271A
Cited
US4008405A
Cited
US4051913A
Cited
US4048673A
Cited
US4047007A
Cited
US4146779A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-12-17 | 1983-06-18 | 1983-12-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-12-17 | 1987-06-18 | 1987-12-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-12-17 | 1991-06-18 | 1991-12-18 | $7700.00 | Window Closed / Lapsed |