Electronic phase locked loop circuit

Claim 2

A phase locked loop circuit comprising: (a) a sawtooth signal generator means having an input for receiving a reference clock signal, said generator means being responsive to said reference clock signal for generating a sawtooth-shaped signal with the same period as said reference clock signal; (b) sample and hold circuit means comprised of: (i) a first MOS transistor having source, drain and gate electrodes, the source electrode being coupled to said sawtooth generator means for receiving said sawtooth-shaped signal and the gate electrode being coupled to receive a digital sampling clock signal of selectively controllable clock rate; (ii) an MOS load transistor; (iii) an MOS source transistor serially coupled to said load transistor, said source transistor having a gate electrode coupled to the drain electrode of said first MOS transistor for receiving samples of said sawtooth-shaped signal and having a Miller capacitance for holding the most current sample of said sawtooth-shaped signal; and (iv) output means coupled to said source transistor for generating a phase detection signal of a magnitude proportional to the magnitude of a sample held by said Miller capacitance; (c) programmable counter means coupled to receive multibit digital commands from a digital processor means for generating said digital sampling clock signal at a clock rate selected according to said multibit digital commands; (d) a voltage-controlled oscillator circuit coupled to the output means of said sample and hold circuit means, said oscillator circuit for generating an output clock signal at a frequency proportional to the magnitude of said phase detection signal; and (e) a feedback loop coupling said voltage-controlled oscillator circuit to said programmable counter means for selectively locking the phase locked loop circuit to a frequency selected by said digital processor means.

Claim 3

A phase locked loop circuit comprising: (a) sawtooth signal generator means including: (i) a resistive means, (ii) a capacitive means serially coupled to said resistive means, and (iii) switching means coupled in parallel with said capacitive means, said switching means having an input coupled to receive a reference clock signal with said switching means being responsive to the voltage levels of said reference clock signal for selectively providing high and low impedance paths in parallel with said capacitive means to generate a sawtooth-shaped signal with the same period as said reference clock signal; (b) sample and hold circuit means having a first input coupled to said sawtooth signal generator means for receiving said sawtooth-shaped signals and a second input for receiving a digital sampling clock signal of a selectable clock rate, said circuit means including: (i) a first MOS transistor having a source coupled to said sawtooth generator means for receiving said sawtooth-shaped signal and a gate coupled to receive said sampling clock signal; (ii) a MOS load transistor; (iii) a MOS source transistor serially coupled to said load transistor, said source transistor having a gate electrode coupled to a drain electrode of said first MOS transistor for receiving samples of said sawtooth-shaped signal and having a Miller capacitance for holding the most current sample of said sawtooth-shaped signal; and (iv) output means coupled to said source transistor for generating a phase detection signal of a magnitude proportional to the magnitude of a sample held by said Miller capacitance; (c) a programmable counter means coupled to receive multibit digital commands from a digital processor means for generating said digital sampling clock signal at a clock rate selected according to said multibit digital commands; (d) a voltage-controlled oscillator circuit coupled to the output means of said sample and hold circuit means, said oscillator circuit for generating an output clock signal at a frequency proportional to the magnitude of said phase detection signal; and (e) a feedback loop coupling said voltage-controlled oscillator circuit to said programmable counter means for selectively locking the phase locked loop circuit to a frequency selected by said digital processor means.

Claim 4

A phase locked loop circuit comprising: (a) sawtooth signal generator means including: (i) a resistive means, (ii) a capacitive means serially coupled to said resistive means, and (iii) switching means coupled in parallel with said capacitive means, said switching means having an input coupled to receive a reference clock signal with said switching means being responsive to the voltage levels of said reference clock signal for selectively providing high and low impedance paths in parallel with said capacitive means to generate a sawtooth-shaped signal with the same period as said reference clock signal; (b) sample and hold circuit means having a first input coupled to said sawtooth signal generator means for receiving said sawtooth-shaped signals and a second input for receiving a digital sampling clock signal of a selectable clock rate, said circuit means including: (i) a first MOS transistor having a source coupled to said sawtooth generator means for receiving said sawtooth-shaped signal and a gate coupled to receive said sampling clock signal; (ii) a MOS load transistor; (iii) a MOS source transistor serially coupled to said load transistor, said source transistor having a gate electrode coupled to a drain electrode of said first MOS transistor for receiving samples of said sawtooth-shaped signal and having a Miller capacitance for holding the most current sample of said sawtooth-shaped signal; and (iv) output means coupled to said source transistor for generating a phase detection signal of a magnitude proportional to the magnitude of a sample held by said Miller capacitance; (c) a programmable counter means coupled to receive multibit digital commands from a digital processor means for generating said digital sampling clock signal at a clock rate selected according to said multibit digital commands; (d) a voltage-controlled oscillator circuit coupled to the output means of said sample and hold circuit means, said oscillator circuit for generating an output clock signal at a frequency proportional to the magnitude of said phase detection signal; and (e) a feedback loop coupling said voltage-controlled oscillator circuit to said programmable counter means for selectively locking the phase locked loop circuit to a frequency selected by said digital processor means.