Triple random error correcting convolutional code

Claim 3

A method according to claim 1, wherein one of said information bits I K and a corresponding parity bit P K are transmitted sequentially.

Claim 6

A method according to claim 3, wherein said inverting step is performed by adding quantities X1, X2, X3, X4, S1 and S2; and by inverting bit I K-12 ' if the sum is greater than three.

Claim 7

A method according to claim 3, wherein after one of said information bits I K ' and the corresponding parity bit P K ' are received, then bit I K-12 ' is inverted as per said condition before additional information bits and parity bits are received.

Claim 8

A method according to claim 5, and further including the step of inverting syndrome bits S K , S K-7 , S K-9 , S K-10 , and S K-11 if said condition is met.

Claim 9

A method according to claim 6, and further including the step of: inhibiting said inverting of said syndrome bits when S K ', S K-1 '. . . S K-12 equal 0111111100101.

Claim 10

Apparatus for transmitting an encoded bit stream containing information bits I K where K=1, 2, . . . comprising: means for generating a parity bit P K for each of said information bits I K ; where P K is the modulo 2 sum of information bits I K , I K-1 , I K-2 , I K-3 , I K-5 , and I K-12 ; and means for transmitting both said information bits I K and said parity bits P K as said encoded bit stream.

Claim 11

Apparatus for transmitting an encoded bit stream containing information bits I K where K=1, 2, . . . comprising: means for generating a parity bit P K for each of said information bits I K ; where P K is the modulo 2 sum of information bits I K , I K-1 , I K-2 , I K-3 , I K-5 , and I K-12 ; and means for transmitting both said information bits I K and said parity bits P K as said encoded bit stream.

Claim 12

Apparatus according to claim 8, wherein said means for generating includes a thirteen bit shift register, means for receiving and shifting said information bits I K , and means for forming a modulo 2 sum of bits I K , I K-1 , I K-2 , I K-3 , I K-5 , and I K-12 in said shift register means; and wherein said means for transmitting includes switching means for alternately passing said information bits I K and corresponding parity bits P K .

Claim 13

Apparatus for decoding transmitted information bits I K from received information bits I K ' and received parity bits P K ' where I K equals I K plus a random error bit e i K ' P K ' equals P K plus a random error bit e p K ' and K=1, 2, . . . comprised of: means for receiving said bits I K ' and P K ' from an external source; means for generating, coupled to said means for receiving, for generating a syndrome bit S K for each of said received bits I K ' where S K is the modulo 2 sum of received bits P K ', I K ', I K-1 ' I K-2 ', I K-3 ', I K-5 ' and I K-12 '; means for forming, coupled to said means for generating, for forming the modulo 2 sums X1=S K +S K-2 ' X2=S K-1 +S K-4 +S K-7 ' X3=S K-5 +S K-5 +S K-6 +S K-10 ' X4=S K-8 +S K-9 means for determining, coupled for said means for forming, for determining when more than three of said modulo 2 sums X1, X2, X3, X4, S K-11 and S K-12 equal one, and means for inverting, responsive to said means for determining, for inverting bit I K-12 ' on the condition that more than three of said modulo 2 sums X1, X2, X3, X4, S K-11 and S K-12 equal one.

Claim 14

Apparatus for decoding transmitted information bits I K from received information bits I K ' and received parity bits P K ' where I K equals I K plus a random error bit e i K ' P K ' equals P K plus a random error bit e p K ' and K=1, 2, . . . comprised of: means for receiving said bits I K ' and P K ' from an external source; means for generating, coupled to said means for receiving, for generating a syndrome bit S K for each of said received bits I K ' where S K is the modulo 2 sum of received bits P K ', I K ', I K-1 ' I K-2 ', I K-3 ', I K-5 ' and I K-12 '; means for forming, coupled to said means for generating, for forming the modulo 2 sums X1=S K +S K-2 ' X2=S K-1 +S K-4 +S K-7 ' X3=S K-5 +S K-5 +S K-6 +S K-10 ' X4=S K-8 +S K-9 means for determining, coupled for said means for forming, for determining when more than three of said modulo 2 sums X1, X2, X3, X4, S K-11 and S K-12 equal one, and means for inverting, responsive to said means for determining, for inverting bit I K-12 ' on the condition that more than three of said modulo 2 sums X1, X2, X3, X4, S K-11 and S K-12 equal one.

Claim 15

Apparatus according to claim 10, wherein said means for determining includes means for adding quantities X1, X2, X3, X4; S K-11 and S K-12 and means for generating a digital signal indicating if the sum is greater than three.

Claim 16

Apparatus according to claim 10, wherein said means for generating includes thirteen bit shift register means for receiving and shifting said bits I K ', and modulo 2 adder means coupled to said shift register means for forming bit S K from said bits in said shift register means.

Claim 17

Apparatus according to claim 10, wherein said means for forming includes thirteen bit shift register means for receiving and shifting said bits S K , and modulo 2 adder means coupled to said shift register means for forming X1, X2, X3 and X4.

Claim 18

Apparatus according to claim 10, and further including means for inverting, coupled to said means for determining, for inverting syndrome bits S K ', S K-7 ', S K-9 ', S K-10 , and S K-11 when said means for determining determines that more than three of said modulo 2 sums equal one.

Claim 19

Apparatus according to claim 14 and further including means for determining is bits S K , S K-1 , . . . S K-12 equal 0111111100101, and means for inhibiting said means for inverting said syndrome bits if bits S K , S K-1 , . . . S K-12 equal 0111111100101.