US4193126A
Expired / Lapsed
US
⏱️ 0.0 years remaining
I2 L Ram unit
Assignee: Arris Technology Inc
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Filing: 1978-12-04
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Granted: 1980-03-11
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Expires: 1998-12-04
Abstract
Abstract The memory unit comprises a plurality of bipolar inverter transistors and an equal number of injector transistors, each of which acts as a current source for a different one of the inverter transistors. Means are provided for cross-coupling a first and a second of the inverter transistors to form a flip-flop. Third, fourth and fifth inverter transistors provide input data flow from the data line to the cross-coupled first and second inverters, in accordance with a write control sixth inverter transistor connected to receive a write signal. A seventh inverter transistor provides data output flow between the cross-coupled first and second inverter transistors and the data line in accordance with the read control eighth inverter transistor connected to receive a read signal.
Inventors
- 👤 Kent F. Smith
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 21:47
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/411; G11C11/4113; H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/288; H10; H10B; H10B10/00; H10B10/10
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
185 words
A memory unit for use in a memory circuit of the type having a power source, a data input/output line, a read line and a write line, said unit comprising a given number of inverter transistors, each having a base terminal, an emitter terminal operably connected to ground, and one or more collector terminals and said given number of injector transistors, each having a base terminal operably connected to ground, an emitter terminal operably connected to the power source and a collector terminal operably connected to the base terminal of a different one of said inverter transistors, respectively, means for cross-coupling a first and a second of said inverter transistors to form a flip-flop configuration, the state of said flip-flop being determined by the data stored therein and means operably interposed between and operably connected to the read, write and data lines, on the one hand, and said cross-coupled first and second inverter transistors, on the other hand, to control data flow between the data line and said cross-coupled first and second inverter transistors in accordance with signals applied on the read and write lines.
Claim 2
Dependent Claim
185 words
A memory unit for use in a memory circuit of the type having a power source, a data input/output line, a read line and a write line, said unit comprising a given number of inverter transistors, each having a base terminal, an emitter terminal operably connected to ground, and one or more collector terminals and said given number of injector transistors, each having a base terminal operably connected to ground, an emitter terminal operably connected to the power source and a collector terminal operably connected to the base terminal of a different one of said inverter transistors, respectively, means for cross-coupling a first and a second of said inverter transistors to form a flip-flop configuration, the state of said flip-flop being determined by the data stored therein and means operably interposed between and operably connected to the read, write and data lines, on the one hand, and said cross-coupled first and second inverter transistors, on the other hand, to control data flow between the data line and said cross-coupled first and second inverter transistors in accordance with signals applied on the read and write lines.
Claim 3
Dependent Claim
27 words
The unit of claim 1, wherein said data flow control means comprises read control means, write control means, data input flow means, and data output flow means.
Claim 4
Dependent Claim
27 words
The unit of claim 2, wherein said data input flow means is operably connected between the data flow line and said cross-coupled first and second inverter transistors.
Claim 5
Dependent Claim
45 words
The unit of claim 3, wherein said write control means is operatively interposed between said data input flow means and said cross-coupled first and second inverter transistors and serves to operatively connect said data input flow means with said cross-coupled first and second inverter transistors.
Claim 6
Dependent Claim
27 words
The unit of claim 2, wherein said data output flow means is operably connected between the data flow line and said cross-coupled first and second inverter transistors.
Claim 7
Dependent Claim
45 words
The unit of claim 5, wherein said read control means is operatively interposed between said data output flow means and said cross-coupled first and second inverter transistors and serves to operatively connect said data output flow means with said cross-coupled first and second inverter transistors.
Claim 8
Dependent Claim
109 words
The unit of claim 2, wherein said data input flow means comprises a third inverter transistor, the base terminal of which is connected to the data flow line; a fourth inverter transistor, the base terminal of which is connected, through a first junction, to the collector of said third inverter transistor; and a fifth inverter transistor, the base terminal of which is connected, through a second junction, to a collector terminal of said fourth inverter transistor, the other collector of said fourth inverter transistor and the collector terminal of said fifth inverter transistor being operably connected to the collector terminals of said cross-coupled first and second inverter transistors, respectively.
Claim 9
Dependent Claim
45 words
The unit of claim 7, wherein said write control means comprises a sixth inverter transistor, the base terminal of which is operably connected to the write line and first and second collector terminals of which are operably connected to said first and second junctions, respectively.
Claim 10
Dependent Claim
53 words
The unit of claim 2, wherein said data output flow means comprises a seventh inverter transistor having a base terminal operably connected, through a third junction, to a collector terminal of one of said cross-coupled first and second inverter transistors and a collector terminal of which is operably connected to the data line.
Claim 11
Dependent Claim
38 words
The unit of claim 9, wherein said read control means comprises an eighth inverter transistor, the base of which is operably connected to the read line and the collector of which is operably connected to said third junction.
Claim 12
Dependent Claim
17 words
The unit of claim 1, wherein each of said inverter transistors comprises a vertical NPN bipolar transistor.
Claim 13
Dependent Claim
15 words
The unit of claim 1, wherein said injector transistor comprises a lateral PNP bipolar transistor.
Claim 14
Dependent Claim
15 words
The unit of claim 11, wherein said injector transistor comprises a lateral PNP bipolar transistor.
References Cited (Backward Citations)
US3177374A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-03-11 | 1983-09-10 | 1984-03-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-03-11 | 1987-09-10 | 1988-03-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-03-11 | 1991-09-10 | 1992-03-11 | $7700.00 | Window Closed / Lapsed |