Digital hysteresis circuit

Claim 1

In a successive ranged analog/digital converter having a switchable gain amplifier chain and an n bit parallel analog/digital converter, the improvement of an automatic bias adjustment circuit with hunting elimination means, said automatic bias adjustment circuit comprising a first up/down counter means for counting between extremum states in response to enable and up/down input signals and having a pre-set state intermediate said extremum states, said first up/down counter means generating an enable output pulse and a reset pulse for each extremum state count, means for re-setting said first up/down counter means to said pre-set state in response to each said reset pulse, a second up/down counter means receiving enable pulses from said first up/down counter means, digital/analog converter means driven by said second up/down counter means and providing bias correction signals in response thereto, a logic circuit for developing from said n bit parallel analog/digital converter first and second logic functions, said logic functions defining a given sub-range, and up/down counter actuating means receiving said first and second logic functions and clock signals, said actuating means enabling said first up/down counter means in response to said first logic function and effecting counting thereby in a direction dictated by the state of said second logic function.