Charge transfer device stored with fixed information

Claim 1

A charge transfer device, comprising: a charge supplying source section; a charge transfer section coupled at one end to said charge supplying source section and including a semiconductor substrate of a first conductivity type, an insulation layer provided on said semiconductor substrate and a plurality of charge transfer electrodes provided on said insulation layer, each adapted to be supplied with a gate signal; an output section coupled to the other end of said charge transfer section; said charge transfer section including a plurality of first semiconductor regions in which first fixed information is stored, and a plurality of second semiconductor regions in which second fixed information is stored, each of said first and second semiconductor regions being serially disposed upon said semiconductor substrate between said source section and said output section; each of said first semiconductor regions including a first pair of subregions and a second pair of subregions disposed adjacent to said first pair of subregions, each of said first and second pairs of subregions including a first type subregion and a second type subregion disposed adjacent to said first type subregion with each said subregion having a discrete charge transfer electrode disposed thereover; each of said second semiconductor regions including a third pair of subregions and a fourth pair of subregions disposed adjacent to said third pair of subregions, each of said third pair of subregions including a first type subregion and a second type subregion disposed adjacent to said first type subregion, each of said fourth pair of subregions including a first type subregion and a third type subregion disposed adjacent to said first type subregion, each of said first, second, and third type subregions having a discrete charge transfer electrode disposed thereover; each of said discrete charge transfer electrodes disposed over said first and third pairs of subregions adapted to be supplied with a first gating signal voltage, and each of said discrete charge transfer electrodes disposed over said second and fourth pairs of subregions adapted to be supplied with a second gating signal voltage; each of said subregions exhibiting a gate voltage-surface potential characteristic curve such that the characteristic curves for said first type subregion and for said third type subregion are approximately parallel and the characteristic curve of said second type subregion is such that it intersects with the characteristic curves of said first and said third type subregions.