Circuit arrangement for the digital correction of time base errors of a television signal using variable addressing of a memory

Claim 1

A circuit arrangement for the digital correction of time base errors of a television signal, said circuit comprising an analog to digital converter for converting said television signal into digital television signals with a specific clock frequency, a random access memory device with a given number of addresses coupled to said converter, a digital to analog converter coupled to said memory for reconverting said digital signals into an analog television signal, an address circuit coupled to the memory device for writing the digital television signals into the addresses of the memory device with the clock frequency and for reading at times in between the times of said writing the memory device addresses with the clock frequency, the addresses that are read being selected in accordance with the magnitude and sign of the time base error; an identification circuit for determining the time base error comprising a phase discriminator to which a comparison signal derived from the television signal is applied, said comparison signal being compared with a desired signal; said identification circuit having output means for supplying digital time base error output signals which occur at a given time interval, the ratio of the time interval which is defined by the clock frequency to the given time interval for the formation of the digital time base error signals being an integer, said output means being coupled to the address circuit for controlling the selection of the memory device addresses to be read depending on the number of time intervals contained in the digital time base error signals and defined by the clock frequency with respect to the number of memory device addresses.