US4219834A
Expired / Lapsed
US
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One-device monolithic random access memory and method of fabricating same
Assignee: International Business Machines Corp
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Filing: 1977-11-11
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Granted: 1980-08-26
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Expires: 1997-11-11
Abstract
Abstract A dynamic random access memory is fabricated on a monolithic chip of semiconductor material. The memory is formed of an array of memory cells controlled for reading and writing by word and bit lines which are selectively connected to the cells. Each cell is a single field effect transistor structure having improved electrical charge storage capability. The improved charge storage capability of each cell is provided by an electrical capacitance structure uniquely arranged and formed as an integral portion of the field effect transistor structure. The gate electrode of each field effect transistor structure is connected to a predetermined one of said word lines. The drain of each field effect transistor is connected to a predetermined one of said bit lines. The source of each field effect transistor structure is integrally connected to and forms a portion of the uniquely arranged electrical capacitance structure of the field effect transistor structure. The electrical capacitance or storage node structure of each cell has increased electrical charge storage capacity and may be considered as a single capacitor. The single (storage) capacitor of each cell is provided between the source of the field effect transistor, a source of reference potential (reference plane) and the monolithic semiconductor substrate on which the memory is fabricated. The arrangement of the memory cells, the structure and material of each of the memory cells, and a method of fabricating the entire memory is disclosed. Also disclosed is an improved field effect transistor structure and process for fabricating same. The process of fabrication, cell arrangement and the improved storage node of each memory cell, as structurally fabricated and uniquely arranged, provides a monolithic memory having improved density and operating characteristics.
Inventors
- 👤 Ronald P. Esch
- 👤 Robert M. Folsom
- 👤 Cheng-Yih Liu
- 👤 Vincent L. Rideout
- 👤 Donald A. Soderman
- 👤 G. Thomas Wenning
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 13:24
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; G11C11/4063; G11C11/407; G11C11/409; G11C11/4097; G11C5/00; G11C5/06; G11C5/063; H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/30; H10P; H10P76/00; H10P76/40
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
338 words
In a read/write monolithic memory having n×m like memory cells, said memory cells being arranged in n columns and m rows, n word lines respectively connected to the m memory cells of a discrete one of said n columns, m bit lines respectively connected to the n memory cells of a discrete one of said m rows, said memory comprising: (a) a substrate of semiconductor material of a first conductivity type having at least one planar surface; (b) m diffused bit lines of a second conductivity type respectively lying on and extending into said planar surface of said substrate, said m diffused bit lines extending in a row direction, said m diffused bit lines being uniformly spaced one from another on said planar surface of said substrate; (c) m/2 doped polysilicon reference planes, each of said planes extending in a row direction between discrete first and second ones of said m diffused bit lines, each said m/2 doped polysilicon planes being generally inverted u-shaped in cross section and being separated from the surface of said substrate by an oxide layer of non-uniform thickness; (d) n×m like memory cells, each said memory cell including a drain, a gate, a source and an integrated capacitor, said memory cells being arranged in n columns and m rows, each of said m diffused bit lines integrally providing the drain electrode of its n associated memory cells, each of said n word lines being connected to the gate of its m associated memory cells, said integrated capacitor of each memory cell having as a first capacitive plate at least a portion of the source of the memory cell, and as a second capacitive plate a portion of one of said m/2 reference planes, said portion of the reference plane overlying and being dielectrically spaced from the first plate by said oxide layer, whereby each of said m/2 doped polysilicon reference planes provides the second plate of the integrated capacitors of the memory cells connected to the two diffused bit lines adjacently spaced thereto.
Claim 2
Dependent Claim
338 words
In a read/write monolithic memory having n×m like memory cells, said memory cells being arranged in n columns and m rows, n word lines respectively connected to the m memory cells of a discrete one of said n columns, m bit lines respectively connected to the n memory cells of a discrete one of said m rows, said memory comprising: (a) a substrate of semiconductor material of a first conductivity type having at least one planar surface; (b) m diffused bit lines of a second conductivity type respectively lying on and extending into said planar surface of said substrate, said m diffused bit lines extending in a row direction, said m diffused bit lines being uniformly spaced one from another on said planar surface of said substrate; (c) m/2 doped polysilicon reference planes, each of said planes extending in a row direction between discrete first and second ones of said m diffused bit lines, each said m/2 doped polysilicon planes being generally inverted u-shaped in cross section and being separated from the surface of said substrate by an oxide layer of non-uniform thickness; (d) n×m like memory cells, each said memory cell including a drain, a gate, a source and an integrated capacitor, said memory cells being arranged in n columns and m rows, each of said m diffused bit lines integrally providing the drain electrode of its n associated memory cells, each of said n word lines being connected to the gate of its m associated memory cells, said integrated capacitor of each memory cell having as a first capacitive plate at least a portion of the source of the memory cell, and as a second capacitive plate a portion of one of said m/2 reference planes, said portion of the reference plane overlying and being dielectrically spaced from the first plate by said oxide layer, whereby each of said m/2 doped polysilicon reference planes provides the second plate of the integrated capacitors of the memory cells connected to the two diffused bit lines adjacently spaced thereto.
Claim 3
Dependent Claim
361 words
In a read/write monolithic memory having n×m like memory cells, said memory cells being arranged in n groups of memory cells, each group including m memory cells, n word lines respectively connected to the m memory cells of a discrete one of said n groups, m bit lines respectively connected to a discrete one of the memory cells of each of said n groups of memory cells, said memory comprising: (a) a substrate of semiconductor material of a first conductivity type having at least one planar surface; (b) m diffused bit lines of a second conductivity type respectively lying on and extending into said planar surface of said substrate, said m diffused bit lines extending in a columnar direction, said m diffused bit lines being spaced one from another on said planar surface of said substrate; (c) m/2 doped polysilicon reference planes, each of said planes extending in a columnar direction between discrete first and second ones of said m diffused bit lines, each of said m/2 doped polysilicon planes being generaly u-shaped in cross sectional configuration, and being separated from the surface of said substrate by an oxide layer of non-uniform thickness; (d) n×m single device memory cells, each said memory cell including a drain, a gate, a source and an integrated capacitor, each of said m diffused bit lines integrally providing the drain electrode for n associated memory cells, each of said n word lines being connected to the gate of m associated memory cells, said integrated capacitor of each memory cell having as a first capacitive plate at least a portion of the source of the memory cell, and as a second capacitive plate a portion of one of said m/2 reference planes, said portion of the reference plane overlying and being dielectrically spaced from the first plate by a relatively thin portion of said oxide layer, whereby each of said m/2 doped polysilicon reference planes provides the second plate of the integrated capacitors of the memory cells connected to the two diffused bit lines adjacently spaced thereto and each said m/2 doped polysilicon reference planes electrically connects in common the second plate of the capacitors formed therein.
Claim 4
Dependent Claim
361 words
In a read/write monolithic memory having n×m like memory cells, said memory cells being arranged in n groups of memory cells, each group including m memory cells, n word lines respectively connected to the m memory cells of a discrete one of said n groups, m bit lines respectively connected to a discrete one of the memory cells of each of said n groups of memory cells, said memory comprising: (a) a substrate of semiconductor material of a first conductivity type having at least one planar surface; (b) m diffused bit lines of a second conductivity type respectively lying on and extending into said planar surface of said substrate, said m diffused bit lines extending in a columnar direction, said m diffused bit lines being spaced one from another on said planar surface of said substrate; (c) m/2 doped polysilicon reference planes, each of said planes extending in a columnar direction between discrete first and second ones of said m diffused bit lines, each of said m/2 doped polysilicon planes being generaly u-shaped in cross sectional configuration, and being separated from the surface of said substrate by an oxide layer of non-uniform thickness; (d) n×m single device memory cells, each said memory cell including a drain, a gate, a source and an integrated capacitor, each of said m diffused bit lines integrally providing the drain electrode for n associated memory cells, each of said n word lines being connected to the gate of m associated memory cells, said integrated capacitor of each memory cell having as a first capacitive plate at least a portion of the source of the memory cell, and as a second capacitive plate a portion of one of said m/2 reference planes, said portion of the reference plane overlying and being dielectrically spaced from the first plate by a relatively thin portion of said oxide layer, whereby each of said m/2 doped polysilicon reference planes provides the second plate of the integrated capacitors of the memory cells connected to the two diffused bit lines adjacently spaced thereto and each said m/2 doped polysilicon reference planes electrically connects in common the second plate of the capacitors formed therein.
Claim 5
Dependent Claim
28 words
In a read/write monolithic memory as recited in claim 2, wherein n and m are respectively positive integer even numbers, each having a magnitude of at least 128.
References Cited (Backward Citations)
US3811076A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-08-26 | 1984-02-25 | 1984-08-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-08-26 | 1988-02-25 | 1988-08-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-08-26 | 1992-02-25 | 1992-08-26 | $7700.00 | Window Closed / Lapsed |