US4221977A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Static I2 L ram
Assignee: Motorola Solutions Inc
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Filing: 1978-12-11
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Granted: 1980-09-09
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Expires: 1998-12-11
Abstract
Abstract A unique topography of I 2 L bipolar semiconductor elements provides Read-Write Random Access Memory (RAM) with very high packing density, low cost, and good power and speed characteristics and with a very simple metallization pattern.
Inventors
- 👤 Ward D. Parkinson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 19:32
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/411; G11C11/4113; H; H10; H10B; H10B10/00; H10B10/10
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
255 words
A plurality of I 2 L semiconductor memory cell circuits on a chip for selection by a plurality of select lines, each of said plurality of memory cells comprising in combination; a first transistor of a first semiconductor type said first transistor having an emitter, a base and a collector; a second transistor of said first semiconductor type said second transistor having an emitter, a base and a collector; a third transistor of a second semiconductor type, said third transistor having a first and a second collector, a base and an emitter; a fourth transistor of said second semiconductor type; said fourth transistor having a first and a second collector, a base and an emitter, said emitter of said first transistor being connected to said first collector of said third transistor and to a first of the pluality of select lines, said collector of said first transistor being connected to said second collector of said third transistor and to said base of said fourth transistor, said base of said first transistor being connected to said base of said second transistor, to said emitter of said third transistor, to said emitter of said fourth transistor and to a third of the plurality of select lines, said emitter of said second transistor being connected to said first collector of said fourth transistor and to a second of the plurality of select lines and said collector of said second transistor being connected to said second collector of said fourth transistor and to said base of said third transistor.
Claim 2
Dependent Claim
255 words
A plurality of I 2 L semiconductor memory cell circuits on a chip for selection by a plurality of select lines, each of said plurality of memory cells comprising in combination; a first transistor of a first semiconductor type said first transistor having an emitter, a base and a collector; a second transistor of said first semiconductor type said second transistor having an emitter, a base and a collector; a third transistor of a second semiconductor type, said third transistor having a first and a second collector, a base and an emitter; a fourth transistor of said second semiconductor type; said fourth transistor having a first and a second collector, a base and an emitter, said emitter of said first transistor being connected to said first collector of said third transistor and to a first of the pluality of select lines, said collector of said first transistor being connected to said second collector of said third transistor and to said base of said fourth transistor, said base of said first transistor being connected to said base of said second transistor, to said emitter of said third transistor, to said emitter of said fourth transistor and to a third of the plurality of select lines, said emitter of said second transistor being connected to said first collector of said fourth transistor and to a second of the plurality of select lines and said collector of said second transistor being connected to said second collector of said fourth transistor and to said base of said third transistor.
Claim 3
Dependent Claim
86 words
The memory cell circuit according to claim 1 wherein said base of said third transistor and said collector of said second transistor are formed in a first isolated layer of a semiconductor chip, said base of said fourth transistor and said collector of said first transistor are formed in a second isolated layer of said semiconductor chip and said base of said first and second transistors and said emitters of said third and fourth transistors are formed in an isolated epitaxial layer of said semiconductor chip.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-09-09 | 1984-03-10 | 1984-09-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-09-09 | 1988-03-10 | 1988-09-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-09-09 | 1992-03-10 | 1992-09-09 | $7700.00 | Window Closed / Lapsed |