Loss of clock detector circuit

Claim 2

Semiconductor apparatus comprising: (a) an MOS differentiator (Δ) having an input terminal; (b) an MOS thresholding amplifier (A) having an input terminal connected to an output terminal of the differentiator (Δ); (c) an MOS unidirectional current inhibitor (D) having an input terminal connected to an output terminal of the amplifier (A); (d) an MOS storage capacitor (C) having one terminal connected to an output terminal of the inhibitor (D); (e) a leakage current source (J L ) connected to said one terminal for providing a leakage current thereto if and only if the charge on said terminal is above a threshold, said inhibitor (D) directed for delivering charge in a direction tending to charge said one terminal and said leakage current being in a direction tending to discharge said one terminal; whereby the voltage level at said one terminal is a binary indication of whether or not clock pulse voltage is being applied to the input terminal of the differentiator (Δ).

Claim 3

Semiconductor apparatus which comprises: (a) a first MOS voltage shifting device (I 1 ) having an input terminal for the application thereto of a clock pulse voltage source; (b) an MOS differentiator (Δ) having an input terminal connected to an output terminal of the first device (I 1 ); (c) an MOS thresholding amplifier (A) having an input terminal connected to an output terminal of the differentiator (Δ); (d) an MOS unidirectional current inhibitor (D) having an input terminal connected to an output terminal of the differentiator (Δ); (e) an MOS storage capacitor (C) having one terminal connected to an output terminal of the inhibitor (D); (f) a leakage current source connected to said one terminal for providing a leakage current thereto if and only if the charge on said terminal is above a threshold, said inhibitor (D) directed for delivering charge in a direction tending to charge said one terminal and said leakage current being in a direction tending to discharge said one terminal; whereby the voltage level at said one terminal is a binary indication of whether or not the clock pulse voltage source is operative.

Claim 4

Semiconductor apparatus which comprises: (a) a first MOS voltage shifting device (I 1 ) having an input terminal for the application thereto of a clock pulse voltage source; (b) an MOS differentiator (Δ) having an input terminal connected to an output terminal of the first device (I 1 ); (c) an MOS thresholding amplifier (A) having an input terminal connected to an output terminal of the differentiator (Δ); (d) an MOS unidirectional current inhibitor (D) having an input terminal connected to an output terminal of the differentiator (Δ); (e) an MOS storage capacitor (C) having one terminal connected to an output terminal of the inhibitor (D); (f) a leakage current source connected to said one terminal for providing a leakage current thereto if and only if the charge on said terminal is above a threshold, said inhibitor (D) directed for delivering charge in a direction tending to charge said one terminal and said leakage current being in a direction tending to discharge said one terminal; whereby the voltage level at said one terminal is a binary indication of whether or not the clock pulse voltage source is operative.

Claim 5

Apparatus according to claim 2 which further comprises a second MOS voltage shifting device I 2 whose input terminal is connected to said one terminal, whereby the voltage level at an output terminal of said second device I 2 is a binary output indicative of interruption of said clock pulse input.

Claim 6

Apparatus according to claim 3 in which said second device is a voltage inverter.

Claim 7

Apparatus according to claim 2 in which said first device (I 1 ) is an MOS inverter.

Claim 8

Apparatus according to claim 2 in which said inhibitor (D) is an MOS field effect transistor whose gate electrode is connected to its drain.

Claim 9

Semiconductor apparatus comprising: (a) a first MS transistor (T 1 ) whose source is connected to a first node N 1 ; (b) a second MOS transistor (T 2 ), characterized by a high transconductance at least ten times that of the first transistor (T 1 ), the drain of T 2 being connected to said first node (N 1 ), and the gate electrode of T 2 being connected to an input node (N 2 ); (c) a third MOS transistor (T 3 ) whose source is connected to its drain and whose gate electrode is connected to the first node (N 1 ); (d) a fourth MOS transistor (T 4 ), characterized in its "on" state by a fourth impedance, whose drain is connected to the drain of the third transistor (T 3 ); (e) a fifth MOS transistor (T 5 ) whose gate electrode is connected to the drain of the fourth transistor (T 4 ); (f) a sixth MOS transistor (T 6 ) whose source is connected to the drain of the fifth transistor (T 5 ), the transconductance of T 5 being at least ten times that of T 6 ; (g) a seventh MOS transistor (T 7 ) whose source is connected to the drain of an eighth MOS transistor (T 8 ), the gate electrode of said eighth transistor being connected to the drain of the fifth transistor (T 5 ), the transconductance of T 8 being at least ten times that of T 7 ; (h) a ninth MOS transistor (T 9 ) whose gate electrode is connected to its drain and to the drain of the eighth transistor (T 8 ); (i) a tenth MOS transistor (T 10 ) whose drain is connected to the source of the ninth transistor (T 9 ) and whose gate electrode is connected to the drain of an eleventh MOS transistor (T 11 ) and to the source of a twelfth MOS transistor (T 12 ), the transconductance of T 11 being at least ten times that of T 12 ; (j) a thirteenth MOS transistor (T 13 ) whose source is connected to its drain and whose gate electrode is connected to the drain of the tenth transistor (T 10 ).

Claim 10

Semiconductor apparatus comprising: (a) a first MS transistor (T 1 ) whose source is connected to a first node N 1 ; (b) a second MOS transistor (T 2 ), characterized by a high transconductance at least ten times that of the first transistor (T 1 ), the drain of T 2 being connected to said first node (N 1 ), and the gate electrode of T 2 being connected to an input node (N 2 ); (c) a third MOS transistor (T 3 ) whose source is connected to its drain and whose gate electrode is connected to the first node (N 1 ); (d) a fourth MOS transistor (T 4 ), characterized in its "on" state by a fourth impedance, whose drain is connected to the drain of the third transistor (T 3 ); (e) a fifth MOS transistor (T 5 ) whose gate electrode is connected to the drain of the fourth transistor (T 4 ); (f) a sixth MOS transistor (T 6 ) whose source is connected to the drain of the fifth transistor (T 5 ), the transconductance of T 5 being at least ten times that of T 6 ; (g) a seventh MOS transistor (T 7 ) whose source is connected to the drain of an eighth MOS transistor (T 8 ), the gate electrode of said eighth transistor being connected to the drain of the fifth transistor (T 5 ), the transconductance of T 8 being at least ten times that of T 7 ; (h) a ninth MOS transistor (T 9 ) whose gate electrode is connected to its drain and to the drain of the eighth transistor (T 8 ); (i) a tenth MOS transistor (T 10 ) whose drain is connected to the source of the ninth transistor (T 9 ) and whose gate electrode is connected to the drain of an eleventh MOS transistor (T 11 ) and to the source of a twelfth MOS transistor (T 12 ), the transconductance of T 11 being at least ten times that of T 12 ; (j) a thirteenth MOS transistor (T 13 ) whose source is connected to its drain and whose gate electrode is connected to the drain of the tenth transistor (T 10 ).

Claim 11

Apparatus according to claim 7 which further includes means for producing an output voltage level corresponding to the voltage level on the gate electrode of T 13 .

Claim 12

Apparatus according to claim 8 in which said means comprises fourteenth and fifteenth MOS transistors (T 14 and T 15 ) the ratio of whose transconductance is less than 1/10, the source of the fourteenth transistor (T 14 ) being connected to the drain of the fifteenth transistor (T 15 ), the gate electrode of the fifteenth transistor (T 15 ) being connected to the gate electrode of the thirteenth transistor (T 13 ), and the drain of the fifteenth transistor (T 15 ) being connected to an output node (N 0 ), whereby in response to a clock pulse source applied to the gate electrode of the second transistor (T 2 ), the voltage level at the drain of the fifteenth transistor (T 15 ) is a binary indication of whether or not the clock pulse source is or is not interrupted.