US4236087A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable bus driver isolation
Assignee: Unisys Corp
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Filing: 1978-10-30
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Granted: 1980-11-25
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Expires: 1998-10-30
Abstract
Abstract A method of and an apparatus for selectively isolating digital data bus drivers from digital data busses for fault recovery and diagnostic purposes. The digital data bus drivers may be either transistor-transistor logic (TTL) or emitter coupled logic (ECL). For TTL digital data bus drivers, the input voltage (V CC ) is supplied via a switching power transistor. For ECL digital data bus drivers, the ground connection (V CC1 ) is made via a switching power transistor. In either case, the switching power transistor is turned on and off in response to one binary bit in an isolation register coupled to the power transistor via an open collector gate or electromechanical switch. By supplying the V CC (for TTL) or V CC1 (for ECL) connection to each digital data bus driver through a switching power transistor and controlling each switching power transistor through a different binary bit in the isolation register, the isolation (or non-isolation) status of each digital data bus driver may be controlled via the isolation register to permit the digital data bus to operate notwithstanding failures effecting the state of one or more of the digital data bus drivers connected to it.
Inventors
- 👤 David G. Kaminski
- 👤 David F. Grimm
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 13:50
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/20; H04L25/24; G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4063; G06F13/4068; G06F13/4072
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
96 words
A digital data bus driver circuit comprising: an ECL tri-state bus driver; a power transistor having a first electrode coupled to a ground connection of said ECL tri-state bus driver and having a second electrode coupled to ground; means responsively coupled to said power transistor for biasing said power transistor whereby said power transistor may be biased to conduct between said first electrode and said second electrode; and means responsively coupled to said biasing means for determining whether said biasing means will bias said power transistor to conduct between said first electrode and said second electrode.
Claim 2
Dependent Claim
96 words
A digital data bus driver circuit comprising: an ECL tri-state bus driver; a power transistor having a first electrode coupled to a ground connection of said ECL tri-state bus driver and having a second electrode coupled to ground; means responsively coupled to said power transistor for biasing said power transistor whereby said power transistor may be biased to conduct between said first electrode and said second electrode; and means responsively coupled to said biasing means for determining whether said biasing means will bias said power transistor to conduct between said first electrode and said second electrode.
Claim 3
Dependent Claim
52 words
A digital data bus driver circuit according to claim 7 wherein said determining means comprises: a register having a binary bit position whereby a predetermined binary state of said binary bit position determines when said biasing means will bias said power transistor to conduct between said first electrode and said second electrode.
Claim 4
Dependent Claim
113 words
A digital data bus driver circuit comprising: a TTL tri-state bus driver; a power supply having an output capable of powering said TTL tri-state bus driver; a power transistor having a first electrode coupled to a power connection of said TTL tri-state bus driver and having a second electrode coupled to said output of supply; means responsively coupled to said power transistor for biasing said power transistor whereby said power transistor may be biased to conduct between said first electrode and said second electrode; and means responsively coupled to said biasing means for determining whether said biasing means will bias said power transistor to conduct between said first electrode and said second electrode.
Claim 5
Dependent Claim
113 words
A digital data bus driver circuit comprising: a TTL tri-state bus driver; a power supply having an output capable of powering said TTL tri-state bus driver; a power transistor having a first electrode coupled to a power connection of said TTL tri-state bus driver and having a second electrode coupled to said output of supply; means responsively coupled to said power transistor for biasing said power transistor whereby said power transistor may be biased to conduct between said first electrode and said second electrode; and means responsively coupled to said biasing means for determining whether said biasing means will bias said power transistor to conduct between said first electrode and said second electrode.
Claim 6
Dependent Claim
52 words
A digital data bus driver circuit according to claim 9 wherein said determining means comprises: a register having a binary bit position whereby a predetermined binary state of said binary bit position determines when said biasing means will bias said power transistor to conduct between said first electrode and said second electrode.
Claim 7
Independent Claim
53 words
A method of isolating an ECL tri-state bus driver from a digital data bus, comprising: setting a binary bit in a register to a predetermined value; and biasing a power transistor in response to said setting step to cause said power transistor to remove the ground path from said ECL tri-state bus driver.
Claim 8
Independent Claim
53 words
A method of isolating an ECL tri-state bus driver from a digital data bus, comprising: setting a binary bit in a register to a predetermined value; and biasing a power transistor in response to said setting step to cause said power transistor to remove the ground path from said ECL tri-state bus driver.
Claim 9
Independent Claim
50 words
A method of isolating a TTL tri-state bus from a digital data bus comprising: setting a binary bit in a register to a predetermined value; and biasing a power transistor in response to said setting step to cause said power transistor to remove power from said TTL tri-state bus driver.
Claim 10
Independent Claim
50 words
A method of isolating a TTL tri-state bus from a digital data bus comprising: setting a binary bit in a register to a predetermined value; and biasing a power transistor in response to said setting step to cause said power transistor to remove power from said TTL tri-state bus driver.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-11-25 | 1984-05-26 | 1984-11-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-11-25 | 1988-05-26 | 1988-11-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-11-25 | 1992-05-26 | 1992-11-25 | $7700.00 | Window Closed / Lapsed |