US4254367A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital servo circuit
Assignee: Sony Corp
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Filing: 1979-01-11
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Granted: 1981-03-03
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Expires: 1999-01-11
Abstract
Abstract A digital servo circuit which, for example, may be used in a video tape recorder, for controlling the velocity and the phase of movement of a video tape by a capstan which is driven by an electric motor. The circuit includes a frequency generator for generating a pulse signal having a repetition rate that varies in accordance with the velocity of the capstan, and hence of the tape driven thereby an n-bit presettable counter for counting a reference clock signal during an interval corresponding to the repetition rate of the pulse signal, a latch circuit for latching the least significant m output bits of the counter (where m is less than n), a control circuit for controlling the m-bit output from the latch circuit so as substantially to hold the latter output at the minimum level when the n-bit output from the counter is less than a first predetermined value, and at the maximum level when the n-bit output from the counter is more than a second predetermined value, and a digital-to-analog converter for converting the m-bit output from the latch circuit to the corresponding analog signal to drive the motor.
Inventors
- 👤 Hitoshi Sakamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 08:11
CPC Classifications
G; G11; G11B; G11B15/00; G11B15/18; G11B15/46; G11B15/467; H; H02; H02P; H02P23/00; H02P23/18; H02P23/186; H02P23/22; Y; Y10; Y10S; Y10S388/00; Y10S388/907; Y10S388/912
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
181 words
A digital servo circuit for controlling the velocity and phase of a moving member which is driven by an electric motor, said servo circuit comprising: means for generating a reference clock signal; means for generating a first pulse signal having a repetition rate that varies in accordance with the velocity of said moving member; n-bit presettable counter means for counting said reference clock signal during an interval corresponding to said repetition rate of said pulse signal; latch means for latching an output of the m least significant bits of said counter means, where m is less than n; control means for controlling said m-bit output from said latch means so as substantially to hold the latter output at a minimum level when the n-bit count of said counter means is less than a first predetermined value and at a maximum level when said n-bit count of said counter means is more than a second predetermined value; and means for converting said m-bit output from said latch means to a corresponding analog signal with which to control the rotation of said motor.
Claim 2
Dependent Claim
181 words
A digital servo circuit for controlling the velocity and phase of a moving member which is driven by an electric motor, said servo circuit comprising: means for generating a reference clock signal; means for generating a first pulse signal having a repetition rate that varies in accordance with the velocity of said moving member; n-bit presettable counter means for counting said reference clock signal during an interval corresponding to said repetition rate of said pulse signal; latch means for latching an output of the m least significant bits of said counter means, where m is less than n; control means for controlling said m-bit output from said latch means so as substantially to hold the latter output at a minimum level when the n-bit count of said counter means is less than a first predetermined value and at a maximum level when said n-bit count of said counter means is more than a second predetermined value; and means for converting said m-bit output from said latch means to a corresponding analog signal with which to control the rotation of said motor.
Claim 3
Dependent Claim
102 words
A servo circuit according to claim 1, in which said control means comprises a first detecting circuit for detecting an output of the i most significant bits of said counter means, where i equals n minus m, said first detecting circuit generating a first control signal when said i bits are all in the same condition, and a second detecting circuit for detecting an output of at least the l most significant bits of said counter means, where l is greater than i, said second detecting circuit generating a second control signal when said l bits are all in the same condition.
Claim 4
Dependent Claim
14 words
A servo circuit according to claim 2, in which l is less than n.
Claim 5
Dependent Claim
77 words
A servo circuit according to claim 2, in which said control means further comprises a first means controlled by said first control signal for preventing the supply of said m-bit output to said converting means in the absence of the generation of said first control signal and a second means controlled by said second control signal for stopping the supply of said reference clock signal to said counter means when said second control signal is supplied thereto.
Claim 6
Dependent Claim
34 words
A servo circuit according to claim 4, in which said first means comprise means operative for clearing said latch means, and the clearing function of which is rendered inoperative by said first control signal.
Claim 7
Dependent Claim
97 words
A servo circuit according to claim 1, further comprising: means providing a reference phase signal; means for generating a second pulse signal that represents the instantaneous position of said moving member; k-bit counter means for counting said reference clock signal during an interval which corresponds to the phase difference between said second pulse signal and said reference phase signal; and means for loading the k bit output of said second counter means into the least significant k bit positions of said first counter means at an interval corresponding to the repetition rate of said first pulse signal.
Claim 8
Dependent Claim
20 words
A servo circuit according to claim 6, in which k is less than n and k is greater than m.
References Cited (Backward Citations)
US3836756A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-03-02 | 1984-09-01 | 1985-03-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-03-02 | 1988-09-01 | 1989-03-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-03-02 | 1992-09-01 | 1993-03-03 | $7700.00 | Window Closed / Lapsed |