IIL Type semiconductor integrated circuit

Claim 1

A semiconductor integrated circuit device formed in a common semiconductor wafer having a pair of principal surfaces, comprising: a first semiconductor region of a first conductivity type disposed adjacent to one of said principal surfaces, a second semiconductor region of a second conductivity type opposite to said first conductivity type disposed adjacent to said first semiconductor region between said first semiconductor region and the other of said principal surfaces, said first and second semiconductor regions forming a PN junction therebetween, a third semiconductor region of said first conductivity type disposed in said second semiconductor region and adjacent to said other principal surface, a fourth and a fifth semiconductor region of said second conductivity type disposed adjacent to each other, said fourth semiconductor region being disposed adjacent to said second semiconductor region, while the fifth semiconductor region is separated from said second semiconductor region by said fourth semiconductor region, a sixth semiconductor region of said first conductivity type disposed adjacent to said fourth semiconductor region, a seventh semiconductor region of said first semiconductor type disposed adjacent to said fourth semiconductor region, and electrically connected to said sixth semiconductor region, said sixth and seventh regions substantially surrounding said fourth semiconductor region and at least part of said fifth semiconductor region, thereby forming a vertically oriented current path in said fourth semiconductor region, an injection electrode formed on said fifth semiconductor region and electrically isolated from sixth semiconductor region, and means for applying a biasing potential between said injection electrode and said first semiconductor region of such polarity as to forward bias the PN junction between said first and second semiconductor regions.