US4271483A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Delay circuits
Assignee: Independent Broadcasting Authority
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Filing: 1978-07-31
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Granted: 1981-06-02
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Expires: 1998-07-31
Abstract
Abstract Digital delay apparatus for variable delay uses a shift register fixed delay driving a random access memory variable delay. A variable modulus counter controls the read-write addressing, whereby the difference between addresses sets the variable delay of the random access memory. The random access memory capacity is small relative to the shift register for increased efficiency.
Inventors
- 👤 John L. E. Baldwin
- 👤 Terence E. Corbyn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 08:15
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06; H; H03; H03K; H03K5/00; H03K5/13; H03K5/131; H03K5/135; H03K2005/00013; H03K2005/0015; H03K2005/00234; H03K2005/00241; H03K2005/00247; H03K2005/0026
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
266 words
Digital delay apparatus for delaying digital signals by a fixed time equivalent to x+n bits of information, comprising (a) a source of clock signals; (b) shift register means (10) including a data input terminal adapted for connection with a digital signal source, a clock input terminal adapted for connection with said clock signal source for shifting said register means between signal receiving and signal transmitting modes, respectively, and an output terminal, said shift memory means having a given standard capacity (x); (c) random access memory means (11) including a data input terminal connected with the output terminal of said shift register means, a read/write control input terminal connected with said source of clock signals, at least one address control input terminal, and a final output terminal, said random access memory means having a bit capacity that is small relative to that of said shift register means; and (d) addressing means (12) including a variable modulus counter connected with said address control input terminal for controlling the address locations of information stored in said random access memory means, said variable modulus counter having a clock input terminal connected with said source of clock signals, and a data input terminal for setting the counter modulus to a desired delay value (n), said random access memory means and said addressing means being operable by said clock signals to cause the total delay of the output signal appearing at the output terminal of said memory means to equal the sum of the storage capacities of said shift register means and the set delay capacity of said random access memory means.
Claim 2
Dependent Claim
266 words
Digital delay apparatus for delaying digital signals by a fixed time equivalent to x+n bits of information, comprising (a) a source of clock signals; (b) shift register means (10) including a data input terminal adapted for connection with a digital signal source, a clock input terminal adapted for connection with said clock signal source for shifting said register means between signal receiving and signal transmitting modes, respectively, and an output terminal, said shift memory means having a given standard capacity (x); (c) random access memory means (11) including a data input terminal connected with the output terminal of said shift register means, a read/write control input terminal connected with said source of clock signals, at least one address control input terminal, and a final output terminal, said random access memory means having a bit capacity that is small relative to that of said shift register means; and (d) addressing means (12) including a variable modulus counter connected with said address control input terminal for controlling the address locations of information stored in said random access memory means, said variable modulus counter having a clock input terminal connected with said source of clock signals, and a data input terminal for setting the counter modulus to a desired delay value (n), said random access memory means and said addressing means being operable by said clock signals to cause the total delay of the output signal appearing at the output terminal of said memory means to equal the sum of the storage capacities of said shift register means and the set delay capacity of said random access memory means.
Claim 3
Dependent Claim
37 words
Apparatus as defined in claim 1, wherein said random access memory means is of the two address port type, the difference between read and write addresses affording the number of clock pulse delay through said memory means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-06-01 | 1984-12-01 | 1985-06-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-06-01 | 1988-12-01 | 1989-06-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-06-01 | 1992-12-01 | 1993-06-02 | $7700.00 | Window Closed / Lapsed |