US4272307A
Expired / Lapsed
US
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Integrated circuit with I2 L and power transistors and method for making
Assignee: Allegro Microsystems LLC
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Filing: 1979-03-12
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Granted: 1981-06-09
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Expires: 1999-03-12
Abstract
Abstract An integrated circuit has a P-type substrate and two N-type epitaxial layers. P-type isolation walls define pockets in the dual-layer epitaxial material, a power transistor being formed in one and an inverted I 2 L transistor being formed in another of the pockets. An upper buried layer doped with antimony (N-type) at the interface between the two epitaxial layers extends into the outer epitaxial layer forming a N + N holes-barrier junction. This junction is spaced from the depletion region of the normally forward biased base emitter junction by from 0.1 to 0.45 holes-diffusion lengths to provide high emitter efficiency in 0.5 to 5 ohm-cm epitaxial material. The P-type bases of the two kinds of transistors have the same depth but the N-type emitter of the power transistor is shallower than the N-type collector of the inverted transistor although formed earlier. Breakdown voltage of the power transistor is thus enhanced while the base width of the I 2 L transistor is predictable and uniform being substantially determined by late and independent process steps.
Inventors
- 👤 James F. Mayrand
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 23:22
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/65; H10D84/658; H10D84/01; H10D84/0112; H10D84/0116; H10D84/02; H10D84/03; H10D84/038; Y; Y10; Y10S; Y10S148/00; Y10S148/087; Y10S148/088
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
226 words
A method for making an integrated circuit having a power transistor in one epitaxial pocket and an I 2 L transistor in another epitaxial pocket, chronologically comprising: (a) forming first N-type epitaxial layer on a face of a P-type silicon substrate; (b) predoping a portion of the exposed face of said first epitaxial layer with antimony atoms; (c) forming over said first layer a second N-type epitaxial layer; (d) at least partially electrically isolating said one and another pockets in said layers so that said predoped face portion is in said another pocket; (e) forming an N-type emitter region in said one pocket extending into said second layer from the outer surface thereof; (f) heating said substrate, to further expand said emitter, to complete said electrically isolating, and to drive said antimony atoms to form an N-type buried layer at the interface between said layers in said another pocket creating an N + N holes-barrier junction with the unaltered portion of said epitaxial layer; (g) diffusing two P-type base regions extending from the outer surface of and part way through said second epitaxial layer for said power transistor in said one pocket and for said inverted I 2 L transistor in said another pocket, respectively; and (h) diffusing an N-type collector region extending from said surface part way into said I 2 L transistor base region.
Claim 2
Independent Claim
226 words
A method for making an integrated circuit having a power transistor in one epitaxial pocket and an I 2 L transistor in another epitaxial pocket, chronologically comprising: (a) forming first N-type epitaxial layer on a face of a P-type silicon substrate; (b) predoping a portion of the exposed face of said first epitaxial layer with antimony atoms; (c) forming over said first layer a second N-type epitaxial layer; (d) at least partially electrically isolating said one and another pockets in said layers so that said predoped face portion is in said another pocket; (e) forming an N-type emitter region in said one pocket extending into said second layer from the outer surface thereof; (f) heating said substrate, to further expand said emitter, to complete said electrically isolating, and to drive said antimony atoms to form an N-type buried layer at the interface between said layers in said another pocket creating an N + N holes-barrier junction with the unaltered portion of said epitaxial layer; (g) diffusing two P-type base regions extending from the outer surface of and part way through said second epitaxial layer for said power transistor in said one pocket and for said inverted I 2 L transistor in said another pocket, respectively; and (h) diffusing an N-type collector region extending from said surface part way into said I 2 L transistor base region.
Claim 3
Dependent Claim
47 words
The method of claim 1 wherein said electrically isolating includes diffusing P-type impurities into said second epitaxial layer to partially form a PN junctions isolation wall between said pockets and further includes further driving said P-type impurities during said heating to complete the formation of said wall.
Claim 4
Dependent Claim
24 words
The method of claim 1 wherein said forming said N-type emitter region in said one pocket comprises introducing arsenic atoms into said emitter region.
Claim 5
Dependent Claim
65 words
The method of claim 3 wherein said diffusing of said bases includes: providing a mask over said surface having two holes over a portion of the surface areas of said one and another pockets, respectively; predepositing a thin layer of boron atoms on said pocket surface areas; and heating said substrate to drive and diffuse said bases to about the same depth from said surface.
Claim 6
Dependent Claim
35 words
The method of claim 4 wherein said heating to diffuse said bases is at a temperature of about 1130° C. for about 50 minutes to form bases each having a depth of about 2.5 microns.
Claim 7
Dependent Claim
74 words
The method of claim 4 wherein said diffusing of said I 2 L transistor collector comprises: after diffusing said bases, providing a mask over said surface with a hole over a portion of the surface area of said I 2 L transistor base; and heating said substrate in the presence of an N-type impurity to form said collector region having a thickness that is greater than the thickness of said power transistor emitter region.
Claim 8
Dependent Claim
41 words
The method of claim 6 wherein said heating to diffuse said collector is at a temperature of about 1070° C. for about 22 minutes in a phosphorous containing atmosphere to produce a collector region having a thickness of about 2.0 microns.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-06-08 | 1984-12-08 | 1985-06-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-06-08 | 1988-12-08 | 1989-06-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-06-08 | 1992-12-08 | 1993-06-09 | $7700.00 | Window Closed / Lapsed |