US4275465A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Clock rate recovery circuit
Assignee: Alcatel CIT SA
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Filing: 1979-10-30
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Granted: 1981-06-23
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Expires: 1999-10-30
Abstract
Abstract There is a need to recover the clock rate from a received and demodulated binary data signal in order to properly decode the received data. Unfortunately some linear modulation systems used for transmission have the effect of ensuring that there is substantially no frequency component in the received signal at the desired clock rate. Non-linear processing of the received signal (e.g. by a rectifier circuit) is therefore necessary to recover the clock. A simple rectifier circuit system is sensitive to the phase difference between the transmitter and receiver carrier waves. The present recovery circuit (10) requires a quadrature demodulator (9) to provide in-phase and quadrature versions x 1 (t) and x 2 (t) of the received demodulated data signal. Two parallel chains of rectifier circuit (30,31), on/off limiter (32,33), multiplier (34,35) and low pass filter (36,37) act separately on the said versions. Whatever the carrier phase difference, one or other of the chains gives an adequate control signal for a VCO (39). These control signals are summed at (38).
Inventors
- 👤 Michel Lemoussu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 14:39
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/02; H04L27/06; H04L7/00; H04L7/02; H04L7/027
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
255 words
A clock rate recovery circuit for a data transmission system using linear modulation and including a receiver with a synchronous demodulator (9) having two carriers in quadrature and having two outputs, namely an in-phase output (26) and a quadrature output (27), the said circuit comprising: a first rectifier (30) connected to the in-phase output (20) of the demodulator (9); a second rectifier (31) connected to the quadrature output (27) of the demodulator (9); a first two-input/one-output multiplier (34) having one of its inputs connected to the output of the first rectifier (30) and its other input connected to the output of a voltage-controlled oscillator (39); a second two-input/one-output multiplier (35) having one of its inputs connected to the output of the second rectifier (31) and its other input connected to the output of the said voltage-controlled oscillator (39); a first low pass filter (36) connected to the output of the first multiplier (34); a second low pass filter (37) connected to the output of the second multiplier (35); a two-input/one-output summing circuit (38) having one of its inputs connected to the output of the first low pass filter (35) and its other input connected to the output of the second low pass filter (37); and the said voltage-controlled oscillator (39) having a control input connected to the output of the summing circuit (38) and an output delivering a signal at the frequency of the recovered clock rate and connected to one of the inputs of both the first and the second multipliers (34 and 35).
Claim 2
Dependent Claim
255 words
A clock rate recovery circuit for a data transmission system using linear modulation and including a receiver with a synchronous demodulator (9) having two carriers in quadrature and having two outputs, namely an in-phase output (26) and a quadrature output (27), the said circuit comprising: a first rectifier (30) connected to the in-phase output (20) of the demodulator (9); a second rectifier (31) connected to the quadrature output (27) of the demodulator (9); a first two-input/one-output multiplier (34) having one of its inputs connected to the output of the first rectifier (30) and its other input connected to the output of a voltage-controlled oscillator (39); a second two-input/one-output multiplier (35) having one of its inputs connected to the output of the second rectifier (31) and its other input connected to the output of the said voltage-controlled oscillator (39); a first low pass filter (36) connected to the output of the first multiplier (34); a second low pass filter (37) connected to the output of the second multiplier (35); a two-input/one-output summing circuit (38) having one of its inputs connected to the output of the first low pass filter (35) and its other input connected to the output of the second low pass filter (37); and the said voltage-controlled oscillator (39) having a control input connected to the output of the summing circuit (38) and an output delivering a signal at the frequency of the recovered clock rate and connected to one of the inputs of both the first and the second multipliers (34 and 35).
Claim 3
Dependent Claim
19 words
A circuit according to claim 1, wherein the first and second rectifiers (30 and 31) are full wave rectifiers.
Claim 4
Dependent Claim
52 words
A circuit according to claim 1, wherein an on/off limiter (32 and 33) is inserted between the first rectifier (30) and the first multiplier (34) and also between the second rectifier (31) and the second multiplier (35), and in that the first and second multipliers (34,35) are two input "exclusive-or" logic gates.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-06-22 | 1984-12-22 | 1985-06-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-06-22 | 1988-12-22 | 1989-06-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-06-22 | 1992-12-22 | 1993-06-23 | $7700.00 | Window Closed / Lapsed |