US4277291A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for making CMOS field-effect transistors
Assignee: STMicroelectronics SRL
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Filing: 1980-01-21
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Granted: 1981-07-07
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Expires: 2000-01-21
Abstract
Abstract Two patches of silicon nitride are formed above spaced-apart regions of an n-type substrate (2) on an overlying oxide layer (8) of small thickness. Arsenic ions are then implanted through the oxide layer in substrate areas not covered by the patches whereupon one patch (10a) and an adjoining portion of the oxide layer are covered by a photoresist mask (14), leaving unprotected the second patch (10b) and an oxide portion adjacent thereto. The wafer is then bombarded with boron ions, first at a relatively low energy level to penetrate the last-mentioned oxide portion and then at a higher energy level with additional penetration of the second patch (10b) to form a p-well (18) bounded by a p+ guard zone (20); the previously implanted arsenic ions in the unbombarded area form an n+ guard zone (22). Next, the wafer is subjected to a heat treatment in an oxidizing atmosphere with resulting deepening of the guard zones and the p-well and with growth of the oxide layer especially in areas not overlain by the patches whose subsequent removal, together with other oxide portions except for a residue forming two insulating gate supports (24a, 24b), exposes source and drain areas of the p-well (18) and of an n-type pedestal (19) separated therefrom by the guard zones (20, 22). A phosphorus-doped oxide layer (28) is then formed above the p-well whereupon the wafer is heated in a boron atmosphere.
Inventors
- 👤 Gianfranco Cerofolini
- 👤 Giuseppe Ferla
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 19:49
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/102; H10D62/112; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0188; H10D84/02; H10D84/03; H10D84/038; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/0125; H10W10/0126; H10W10/0127; H10W10/10; H10W10/13; Y; Y10; Y10S; Y10S148/00; Y10S148/07
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
326 words
A process for making complementary MOS field-effect transistors with contiguous channel stops in a silicon substrate of one conductivity type overlain by an oxide layer, comprising the steps of: (a) forming a first and second patch of shielding material on said oxide layer above spaced-apart first and second regions of said substrate; (b) injecting impurities of said one conductivity type through said oxide layer into zones of said substrate immediately adjoining said first and second regions, including an intermediate section separating said first and second regions; (c) covering said first patch and at least one immediately adjoining first zone of said oxide layer, including a portion thereof overlying part of said intermediate section, with a masking layer while leaving uncovered said second patch and at least one immediately adjoining second zone of said oxide layer, including a portion thereof overlying another part of said intermediate section; (d) injecting impurities of the opposite conductivity type into said substrate through said second patch and through said second zone in a quantity sufficient to overcompensate the effect of the impurities of said one conductivity type injected into said second zone in step (b) and to implant said impurities of the opposite conductivity type with a relatively high concentration in said uncovered second zone and with a lower concentration in said second region shielded by said second patch; (e) removing said masking layer; (f) subjecting said substrate to a heat treatment with growth of said oxide layer predominantly in areas free from said patches; (g) removing said patches together with underlying portions of said oxide layer, thereby exposing said first and second regions except for a residue of said oxide layer extending across each of said regions and dividing same into source and drain areas while forming an insulating gate support; and (h) introducing impurities of said one conductivity type and of said opposite conductivity type into the source and drain areas of said second and said first region, respectively.
Claim 2
Dependent Claim
326 words
A process for making complementary MOS field-effect transistors with contiguous channel stops in a silicon substrate of one conductivity type overlain by an oxide layer, comprising the steps of: (a) forming a first and second patch of shielding material on said oxide layer above spaced-apart first and second regions of said substrate; (b) injecting impurities of said one conductivity type through said oxide layer into zones of said substrate immediately adjoining said first and second regions, including an intermediate section separating said first and second regions; (c) covering said first patch and at least one immediately adjoining first zone of said oxide layer, including a portion thereof overlying part of said intermediate section, with a masking layer while leaving uncovered said second patch and at least one immediately adjoining second zone of said oxide layer, including a portion thereof overlying another part of said intermediate section; (d) injecting impurities of the opposite conductivity type into said substrate through said second patch and through said second zone in a quantity sufficient to overcompensate the effect of the impurities of said one conductivity type injected into said second zone in step (b) and to implant said impurities of the opposite conductivity type with a relatively high concentration in said uncovered second zone and with a lower concentration in said second region shielded by said second patch; (e) removing said masking layer; (f) subjecting said substrate to a heat treatment with growth of said oxide layer predominantly in areas free from said patches; (g) removing said patches together with underlying portions of said oxide layer, thereby exposing said first and second regions except for a residue of said oxide layer extending across each of said regions and dividing same into source and drain areas while forming an insulating gate support; and (h) introducing impurities of said one conductivity type and of said opposite conductivity type into the source and drain areas of said second and said first region, respectively.
Claim 3
Dependent Claim
77 words
A process as defined in claim 1 wherein the injection of impurities of the opposite conductivity type in step (d) is carried out in two stages, one of said stages involving a bombardment with ions of relatively low intensity unable to penetrate said second patch while traversing said second zone of said oxide layer, the other of said stages involving a bombardment with ions of relatively high intensity penetrating both said oxide layer and said second patch.
Claim 4
Dependent Claim
16 words
A process as defined in claim 1 or 2 wherein said shielding material is silicon nitride.
Claim 5
Dependent Claim
86 words
A process as defined in claim 1 or 2 wherein the introduction of impurities into the source and drain areas of said second region in step (h) is performed by covering said second region with a stratum of silicon oxide doped with impurities of said one conductivity type, heating said substrate to transfer impurities from said stratum to the underlying substrate areas concurrently with a doping of the exposed areas of said first region with impurities of said opposite conductivity type, and then removing said stratum.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-07-06 | 1985-01-05 | 1985-07-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-07-06 | 1989-01-05 | 1989-07-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-07-06 | 1993-01-05 | 1993-07-07 | $7700.00 | Window Closed / Lapsed |