US4289976A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit arrangement for the transmission of digital data
Assignee: Robert Bosch GmbH
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Filing: 1979-11-05
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Granted: 1981-09-15
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Expires: 1999-11-05
Abstract
Abstract A circuit arrangement is described for the transmission of a digital data signal. The circuit arrangement is inserted as an asynchronous interface into the transmission path between digital data handling systems with differing clock frequencies f 1 and f 2 . The circuit arrangement comprises a register 1 of D flip-flops for buffering the input data D 1 . The clocking of the register 1 is performed with a special clock signal f Inter , which is derived from a series circuit of edge controlled R-S and J-K flip-flops 3 and 4 respectively. The result is output data D 2 synchronous with the frequency f 2 .
Inventors
- 👤 Hans-Peter Maly
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 19:25
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/05; H04L7/00; H04L7/0008; H04L7/0012
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
155 words
An interface circuit for the transmission of digital data between digital data handling systems operating with different clock frequencies, the circuit comprising an edge-controlled R-S flip-flop of which the S input is supplied with a first clock signal and the R input is supplied with a second clock signal, a J-K flip-flop of which the J input is maintained at a high logic level and the K input is maintained at a low logic level, the J-K flip-flop having a clock input connected to the output of the R-S flip-flop and a reset input supplied with the second clock signal, and at least one D flip-flop having a clock input connected to the output of the J-K flip-flop and whose D input is arranged to receive digital data at the frequency of the first clock signal, whereby at the output of the D flip-flop digital data is produced in synchronism with the second clock signal.
Claim 2
Dependent Claim
155 words
An interface circuit for the transmission of digital data between digital data handling systems operating with different clock frequencies, the circuit comprising an edge-controlled R-S flip-flop of which the S input is supplied with a first clock signal and the R input is supplied with a second clock signal, a J-K flip-flop of which the J input is maintained at a high logic level and the K input is maintained at a low logic level, the J-K flip-flop having a clock input connected to the output of the R-S flip-flop and a reset input supplied with the second clock signal, and at least one D flip-flop having a clock input connected to the output of the J-K flip-flop and whose D input is arranged to receive digital data at the frequency of the first clock signal, whereby at the output of the D flip-flop digital data is produced in synchronism with the second clock signal.
Claim 3
Dependent Claim
182 words
An interface circuit according to claim 1, wherein the R-S flip-flop comprises a further J-K flip-flop whose J and K inputs are maintained at a high logic level and which is triggered by negative-going edges, the further J-K flip-flop having inverting and non-inverting outputs, a first NAND gate whose output is connected to the clock input of the further J-K flip-flop, a second NAND gate whose output is connected to a first input of the first NAND gate, one of the inputs of the second NAND gate being connected to the non-inverting output of the further J-K flip-flop and the other input of the second NAND gate being connected to the R input of the R-S flip-flop via a first inverter, and a third NAND gate whose output is connected to a second input of the first NAND gate, one of the inputs of the third NAND gate being connected to the inverting output of the further J-K flip-flop and the other input of the third NAND gate being connected to the S input of the R-S flip-flop via a second inverter.
Claim 4
Dependent Claim
47 words
An interface circuit according to claim 1, wherein n D flip-flops are provided for the parallel transmission of a data signal with a word length of n bits, the clock inputs of all of the D flip-flops being connected to the output of the first J-K flip-flop.
Claim 5
Dependent Claim
34 words
An interface circuit according to claim 1, wherein the signal from the output of the first J-K flip-flop is used for indicating further signal processing steps of the data delivered by the D flip-flop.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-09-14 | 1985-03-16 | 1985-09-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-09-14 | 1989-03-16 | 1989-09-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-09-14 | 1993-03-16 | 1993-09-15 | $7700.00 | Window Closed / Lapsed |