US4295209A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programming an IGFET read-only-memory
Assignee: Motors Liquidation Co
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Filing: 1979-11-28
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Granted: 1981-10-13
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Expires: 1999-11-28
Abstract
Abstract An IGFET ROM is programmed later in its process of manufacture. An array of IGFETs having an operable channel region and gate electrode is provided. The gate electrode is penetrable by an ion beam. A first dielectric penetrable by the ion beam is deposited onto the array. A second dielectric not penetrable by the ion beam is then deposited onto the array. Windows are then etched into the second dielectric material but not the first, over channel regions of selected IGFETs. The wafer surface is given an ion implantation to change threshold voltage of those IGFETs selected. A metallization pattern is formed on the second dielectric, with the first dielectric providing an insulating coating for gate electrode portions otherwise exposed within the aforementioned windows.
Inventors
- 👤 William B. Donley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 09:08
CPC Classifications
H; H10; H10B; H10B20/00; H10B20/27; H10B20/30; H10B20/38; H10B20/383; G; G11; G11C; G11C17/00; G11C17/08; G11C17/10; G11C17/12
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
87 words
A programmed read-only-memory comprising: an array of programmable IGFETs on a semiconductor surface; a silicon nitride coating on said surface, with apertures therein for electrically contacting all of said programmable IGFETs; a glass coating on said silicon nitride coating, with apertures therein corresponding to said first-mentioned apertures and additional apertures over channel regions of selected IGFETs; said selected IGFETs having ion implanted channel regions unaffected by gate operating voltage for said read-only-memory; and conductors on said glass coating over said IGFETS through said first-mentioned and corresponding apertures.
Claim 2
Dependent Claim
87 words
A programmed read-only-memory comprising: an array of programmable IGFETs on a semiconductor surface; a silicon nitride coating on said surface, with apertures therein for electrically contacting all of said programmable IGFETs; a glass coating on said silicon nitride coating, with apertures therein corresponding to said first-mentioned apertures and additional apertures over channel regions of selected IGFETs; said selected IGFETs having ion implanted channel regions unaffected by gate operating voltage for said read-only-memory; and conductors on said glass coating over said IGFETS through said first-mentioned and corresponding apertures.
Claim 3
Dependent Claim
114 words
A programmed read-only-memory comprising: an array of programmable IGFETs on a semiconductor surface; a silicon nitride coating on said surface, with apertures therein for electrically contacting drain regions of all said programmable IGFETs; a glass coating on said silicon nitride coating, with apertures therein over all of said silicon nitride drain apertures and also over channel regions of selected IGFETs; said selected IGFETs having ion implanted channels unaffected by gate operating voltages of said read-only-memory; and a metallization layer on said glass coating in a pattern that contacts all of said drain regions, and has portions on said silicon nitride coating instead of an underlying gate electrode over at least some of said channels.
Claim 4
Dependent Claim
114 words
A programmed read-only-memory comprising: an array of programmable IGFETs on a semiconductor surface; a silicon nitride coating on said surface, with apertures therein for electrically contacting drain regions of all said programmable IGFETs; a glass coating on said silicon nitride coating, with apertures therein over all of said silicon nitride drain apertures and also over channel regions of selected IGFETs; said selected IGFETs having ion implanted channels unaffected by gate operating voltages of said read-only-memory; and a metallization layer on said glass coating in a pattern that contacts all of said drain regions, and has portions on said silicon nitride coating instead of an underlying gate electrode over at least some of said channels.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-10-12 | 1985-04-13 | 1985-10-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-10-12 | 1989-04-13 | 1989-10-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-10-12 | 1993-04-13 | 1993-10-13 | $7700.00 | Window Closed / Lapsed |