Memory

Claim 2

A semiconductor memory device comprising a semiconductor substrate of a first conductivity type, first and second semiconductor regions of a second conductivity type provided in said semiconductor substrate, a channel region positioned between said first and second semiconductor regions at the surface of said semiconductor substrate, an insulator film disposed on said channel region, a control electrode disposed on said insulator film, means for generating depletion layers from said first and second semiconductor regions in such a manner that said depletion layers contact with each other to isolate at least a portion of said channel region from said substrate in vertical direction of said semiconductor substrate, means for selectively accumulating majority carriers to said channel region at a density higher than that of said semiconductor substrate, and means for detecting the existence of the accumulation of said majority carriers in said channel region.

Claim 3

The device according to claim 1, wherein said detecting means includes means for generating a punch-through current between said first and second semiconductor regions when said accumulation of said majority carriers do not exist in said channel region.

Claim 4

The device according to claim 1, wherein said accumulating means includes a third semiconductor region of said first conductivity type formed in one of said first and second semiconductor regions.

Claim 5

The device according to claim 1, wherein said accumulating means includes means for operatively separating the contact of said depletion layer so as to feed said majority carriers from said semiconductor substrate to said channel region.

Claim 6

A memory device comprising a plurality of memory word lines, a plurality of digit lines, a plurality of memory cells arranged at respective intersections of said word lines and said digit lines, said memory cell including a first semiconductor region of a first conductivity type, second and third semiconductor regions of a second conductivity type provided in said first semiconductor region, said second semiconductor region being connected to associated one of said word lines, said third semiconductor region being associated one of said digit lines, said second and third semiconductor regions defining a channel region therebetween in said first semiconductor region, an insulator film disposed on said channel region, a conductive layer disposed on said insulator film, and first and second depletion layers extending in said first semiconductor region from said second and third semiconductor regions respectively, said first and second depletion layers being normally overlapped with each other, means for operatively supplying selected one of said word line a first potential which shrinks said first depletion layer, means for operatively supplying selected one of said digit lines with a second potential which shrinks said second depletion region, both of shrinkages of said first and second depletion layers deleting the contact of said first and second depletion layers in each of said memory cells, means for supplying said conductive layer with a third potential which induces majority carriers of said first semiconductor region in said channel region, and means for supplying selected one of said word lines with a fourth potential which causes a punch-through current between said second and third semiconductor regions when said majority carriers are not accumulated in said channel region of selected one of said memory cells.

Claim 7

A memory device comprising a plurality of memory word lines, a plurality of digit lines, a plurality of memory cells arranged at respective intersections of said word lines and said digit lines, said memory cell including a first semiconductor region of a first conductivity type, second and third semiconductor regions of a second conductivity type provided in said first semiconductor region, said second semiconductor region being connected to associated one of said word lines, said third semiconductor region being associated one of said digit lines, said second and third semiconductor regions defining a channel region therebetween in said first semiconductor region, an insulator film disposed on said channel region, a conductive layer disposed on said insulator film, and first and second depletion layers extending in said first semiconductor region from said second and third semiconductor regions respectively, said first and second depletion layers being normally overlapped with each other, means for operatively supplying selected one of said word line a first potential which shrinks said first depletion layer, means for operatively supplying selected one of said digit lines with a second potential which shrinks said second depletion region, both of shrinkages of said first and second depletion layers deleting the contact of said first and second depletion layers in each of said memory cells, means for supplying said conductive layer with a third potential which induces majority carriers of said first semiconductor region in said channel region, and means for supplying selected one of said word lines with a fourth potential which causes a punch-through current between said second and third semiconductor regions when said majority carriers are not accumulated in said channel region of selected one of said memory cells.

Claim 8

The device according to claim 5, wherein said first semiconductor region is common for all of said memory cells.

Claim 9

A semiconductor memory device comprising a plurality of word lines, a plurality of read digit lines, a plurality of write digit lines, a plurality of memory cells including a first semiconductor region of a first conductivity type, a second and a third semiconductor regions of a second conductivity type provided in said first semiconductor region, said second and third semiconductor regions defining a channel region therebetween, said second semiconductor region being connected to one of said read digit lines, a fourth semiconductor region of said first conductivity type provided in said third semiconductor region, said fourth semiconductor region being connected to one of said write digit lines, first and second depletion layers extend from said second and third semiconductor regions respectively, said first and second depletion layers being contacted with each other thereby to isolate said channel region from said first region in vertical direction of said first semiconductor region, an insulator film disposed on said channel region, and a control electrode disposed on said insulator film, said control electrode being connected one of said word lines, and means for supplying selected one of read digit lines with a potential which causes a punch-through current between said second and third semiconductor regions when majority carriers of said first semiconductor region are not accumulated in said channel region.

Claim 10

A semiconductor memory device comprising a plurality of word lines, a plurality of read digit lines, a plurality of write digit lines, a plurality of memory cells including a first semiconductor region of a first conductivity type, a second and a third semiconductor regions of a second conductivity type provided in said first semiconductor region, said second and third semiconductor regions defining a channel region therebetween, said second semiconductor region being connected to one of said read digit lines, a fourth semiconductor region of said first conductivity type provided in said third semiconductor region, said fourth semiconductor region being connected to one of said write digit lines, first and second depletion layers extend from said second and third semiconductor regions respectively, said first and second depletion layers being contacted with each other thereby to isolate said channel region from said first region in vertical direction of said first semiconductor region, an insulator film disposed on said channel region, and a control electrode disposed on said insulator film, said control electrode being connected one of said word lines, and means for supplying selected one of read digit lines with a potential which causes a punch-through current between said second and third semiconductor regions when majority carriers of said first semiconductor region are not accumulated in said channel region.

Claim 11

A memory comprising a semiconductor substrate of one conductivity type, first and second regions of the opposite conductivity type provided in said semiconductor substrate, a channel region located between said first and second regions, a control electrode provided on said channel region via an insulating film, and means for extending depletion layers from said first and second regions so as to isolate said channel region from said semiconductor substrate, and means for selectively accumulating majority carriers of said semiconductor substrate in said channel region, the existence or non-existence of accumulation of said majority carriers in said channel region being made to correspond to the stored information.

Claim 12

A memory comprising a semiconductor substrate of one conductivity type, first and second regions of the opposite conductivity type provided in said semiconductor substrate, a channel region located between said first and second regions, a control electrode provided on said channel region via an insulating film, and means for extending depletion layers from said first and second regions so as to isolate said channel region from said semiconductor substrate, and means for selectively accumulating majority carriers of said semiconductor substrate in said channel region, the existence or non-existence of accumulation of said majority carriers in said channel region being made to correspond to the stored information.