Process for production of integrated MOS circuits with and without MNOS memory transistors in silicon-gate technology

Claim 2

In the process for producing integrated MOS circuits with and without MNOS memory transistors in silicongate technology, and having overlapped contacts using a silicon nitride mask, the improvement comprising: after producing structured SiO 2 layers on a p- or n-doped semiconductor substrate so as to separate active transistor zones in accordance with the so-called LOCOS or isoplanar process, depositing a silicon nitride layer on the entire structure surface and structuring such nitride layer in such a manner that those zones in which gate oxides are to be produced are uncovered, and during a gate oxidation, converting the surface of such structured nitride layer into an oxynitride layer.

Claim 3

In a process as defined in claim 1 wherein a channel ion implanation step is executed, after deposition of such silicon nitride layer on the entire structure surface, through such silicon nitride layer.

Claim 4

A process for producing integrated n-channel and p-channel MOS circuits with and without MNOS memory transistors in silicon-gate technology and having overlapped contacts using a silicon nitride mask, comprising a sequential combination of steps: (a) producing structured SiO 2 layers on a p- or n-doped semiconductor substrate so as to separate active transistor zones in accordance with the so-called LOCOS or isoplanar process; (b) producing a first SiO 2 layer (tunnel oxide) over the entire device surface; (c) depositing a silicon nitride layer over the entire device surface; (d) executing a channel ion implantation; (e) etching said silicon nitride layer so as to produce select nitride-covered substrate zones; (f) executing a gate oxidation step by oxidizing the uncovered n- or p-doped substrate surface and substantially simultaneously oxidizing the surface of said structured silicon nitride layer to form an oxynitride layer; (g) depositing a n + - or p + -doped polysilicon layer over the entire surface and structuring the polysilicon layer in a predetermined manner; (h) executing an ion implantation step so as to produce monocrystalline n + - or p + -doped source and drain zones in said p- or n- doped substrate; (i) oxidizing said structured polysilicon layer to form an SiO 2 layer; (j) producing a second SiO 2 layer (intermediate oxide) onto the entire device surface; (k) etching contact holes so as to form contacts between n + - or p + -doped zones, polysilicon zones and metallic interconnections, respectively, and (l) producing a select pattern of metallic interconnections.

Claim 5

A process for producing integrated n-channel and p-channel MOS circuits with and without MNOS memory transistors in silicon-gate technology and having overlapped contacts using a silicon nitride mask, comprising a sequential combination of steps: (a) producing structured SiO 2 layers on a p- or n-doped semiconductor substrate so as to separate active transistor zones in accordance with the so-called LOCOS or isoplanar process; (b) producing a first SiO 2 layer (tunnel oxide) over the entire device surface; (c) depositing a silicon nitride layer over the entire device surface; (d) executing a channel ion implantation; (e) etching said silicon nitride layer so as to produce select nitride-covered substrate zones; (f) executing a gate oxidation step by oxidizing the uncovered n- or p-doped substrate surface and substantially simultaneously oxidizing the surface of said structured silicon nitride layer to form an oxynitride layer; (g) depositing a n + - or p + -doped polysilicon layer over the entire surface and structuring the polysilicon layer in a predetermined manner; (h) executing an ion implantation step so as to produce monocrystalline n + - or p + -doped source and drain zones in said p- or n- doped substrate; (i) oxidizing said structured polysilicon layer to form an SiO 2 layer; (j) producing a second SiO 2 layer (intermediate oxide) onto the entire device surface; (k) etching contact holes so as to form contacts between n + - or p + -doped zones, polysilicon zones and metallic interconnections, respectively, and (l) producing a select pattern of metallic interconnections.

Claim 6

A process as defined in claim 3 wherein said process is executed in a Si 2 -gate technology and during step (e) gate zones of polysilicon-II transistors to be produced are also opened; after step (i), producing a polysilicon-II layer in a known manner; and executing step (h) after structuring said polysilicon-II layer prior to step (j).

Claim 7

A process for producing integrated n-channel and p-channel MOS circuits without MNOS memory transistors in silicon-gate technology and having overlapped contacts using a silicon nitride mask, comprising a sequential combination of steps: (a) producing structure SiO 2 layers on a p- or n-doped semiconductor substrate so as to separate active transistor zones in accordance with the so-called LOCOS or isoplanar process; (b) depositing a silicon nitride layer over the entire device surface; (c) executing a channel ion implantation; (d) etching said silicon nitride layer so as to produce select nitride-covered substrate zones; (e) executing a gate oxidation step by oxidizing the uncovered n- or p-doped substrate surface and substantially simultaneously oxidizing the surface of said structured silicon nitride layer to form an oxynitride layer; (f) depositing a n + - or p + -doped polysilicon layer over the entire device surface and structuring the polysilicon layer in a predetermined manner; (g) executing an ion implantation step so as to produce monocrystalline n + - or p + -doped source and drain zones in said p- or n-doped substrate; (h) oxidizing said structured polysilicon layer to form an SiO 2 layer; (i) producing a second SiO 2 layer (intermediate oxide) onto the entire device surface; (j) etching contact holes so as to form contacts between n + - or p + -doped zones, polysilicon zones and metallic interconnections, respectively, and (k) producing a select pattern of metallic interconnections.

Claim 8

A process for producing integrated n-channel and p-channel MOS circuits without MNOS memory transistors in silicon-gate technology and having overlapped contacts using a silicon nitride mask, comprising a sequential combination of steps: (a) producing structure SiO 2 layers on a p- or n-doped semiconductor substrate so as to separate active transistor zones in accordance with the so-called LOCOS or isoplanar process; (b) depositing a silicon nitride layer over the entire device surface; (c) executing a channel ion implantation; (d) etching said silicon nitride layer so as to produce select nitride-covered substrate zones; (e) executing a gate oxidation step by oxidizing the uncovered n- or p-doped substrate surface and substantially simultaneously oxidizing the surface of said structured silicon nitride layer to form an oxynitride layer; (f) depositing a n + - or p + -doped polysilicon layer over the entire device surface and structuring the polysilicon layer in a predetermined manner; (g) executing an ion implantation step so as to produce monocrystalline n + - or p + -doped source and drain zones in said p- or n-doped substrate; (h) oxidizing said structured polysilicon layer to form an SiO 2 layer; (i) producing a second SiO 2 layer (intermediate oxide) onto the entire device surface; (j) etching contact holes so as to form contacts between n + - or p + -doped zones, polysilicon zones and metallic interconnections, respectively, and (k) producing a select pattern of metallic interconnections.

Claim 9

A process as defined in claim 5 wherein said process is executed in a Si 2 -gate technology and during step (e) gate zones of polysilicon-II transistors to be produced are also opened; after step (i), producing a polysilicon-II layer in a known manner; and executing step (h) after structuring said polysilicon-II layer prior to step (j).