Method of producing integrated MOS circuits via silicon gate technology

Claim 1

A method of producing integrated n- or p-channel MOS circuits in silicon gate technology with self-adjusting contacts, comprising the steps: (a) producing structure SiO 2 layers (1) on a p- or n-doped semiconductor substrate (2) for separation of active transistor regions according to the so-called LOCOS or isoplanar technique; (b) oxidizing the free p- or n-substrate surfaces so as to attain gate oxidation; (c) depositing a n + - or p + -doped polysilicon layer (4) over the entire structure surface; (d) depositing a silicon nitride layer over the entire structure surface; (e) etching the silicon nitride and the polysilicon layers so as to produce nitride-coated polysilicon regions; (f) producing monocrystalline n + - or p + -doped source and drain regions (5) in the p- or n-doped substrate (2) by ion implantation; (g) producing a SiO 2 layer (6) over the monocrystalline n + - or p + -doped regions (5) by thermal oxidation whereby the oxidation of the polysilicon regions (4) is prevented by the silicon nitride layer positioned over the polysilicon regions (4) and an oxide layer is produced only on the slope surfaces; (h) removing the nitride masking; (i) etching contact holes for formation of contacts between monocrystalline n + - or p + -doped regions (5) and polysilicon regions (4) and/or metal interconnections (12), whereby in the region of buried contacts (9), because of an isotropic etching attack, overhanging polysilicon edges (7) are formed; (j) depositing a n + - or p + -doped polysilicon layer (8) on the entire structure surface whereby the regions (9) beneath the overhanging polysilicon edges (7) are filled with polysilicon (8); (k) depositing a layer of silicon nitride on the entire structure surface; (l) etching the silicon nitride layer except at those locations at which contacts to the metal interconnections (12) are provided; (m) converting the uncovered polysilicon layer (8) into a SiO 2 layer by thermal oxidation, whereby the portions of the polysilicon layer (4) covered with nitride remain unchanged, and, in the region of the buried contacts (9), a polysilicon contact bridge (11) is formed between the monocrystalline n + - or p + -doped regions (5) and the overhanging edges (7) of the polysilicon region (4); (n) removing the nitride masking; and (o) producing a desired metal interconnection pattern (12).

Claim 2

A method of producing integrated n- or p-channel MOS circuits in silicon gate technology with self-adjusting contacts, comprising the steps: (a) producing structure SiO 2 layers (1) on a p- or n-doped semiconductor substrate (2) for separation of active transistor regions according to the so-called LOCOS or isoplanar technique; (b) oxidizing the free p- or n-substrate surfaces so as to attain gate oxidation; (c) depositing a n + - or p + -doped polysilicon layer (4) over the entire structure surface; (d) depositing a silicon nitride layer over the entire structure surface; (e) etching the silicon nitride and the polysilicon layers so as to produce nitride-coated polysilicon regions; (f) producing monocrystalline n + - or p + -doped source and drain regions (5) in the p- or n-doped substrate (2) by ion implantation; (g) producing a SiO 2 layer (6) over the monocrystalline n + - or p + -doped regions (5) by thermal oxidation whereby the oxidation of the polysilicon regions (4) is prevented by the silicon nitride layer positioned over the polysilicon regions (4) and an oxide layer is produced only on the slope surfaces; (h) removing the nitride masking; (i) etching contact holes for formation of contacts between monocrystalline n + - or p + -doped regions (5) and polysilicon regions (4) and/or metal interconnections (12), whereby in the region of buried contacts (9), because of an isotropic etching attack, overhanging polysilicon edges (7) are formed; (j) depositing a n + - or p + -doped polysilicon layer (8) on the entire structure surface whereby the regions (9) beneath the overhanging polysilicon edges (7) are filled with polysilicon (8); (k) depositing a layer of silicon nitride on the entire structure surface; (l) etching the silicon nitride layer except at those locations at which contacts to the metal interconnections (12) are provided; (m) converting the uncovered polysilicon layer (8) into a SiO 2 layer by thermal oxidation, whereby the portions of the polysilicon layer (4) covered with nitride remain unchanged, and, in the region of the buried contacts (9), a polysilicon contact bridge (11) is formed between the monocrystalline n + - or p + -doped regions (5) and the overhanging edges (7) of the polysilicon region (4); (n) removing the nitride masking; and (o) producing a desired metal interconnection pattern (12).