US4327411A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High capacity elastic store having continuously variable delay
Assignee: AT&T Inc
•
Filing: 1980-03-04
•
Granted: 1982-04-27
•
Expires: 2000-03-04
Abstract
Abstract A commutator-type data store (102) is serially connected to a variable length shift register (104). Data is first written in the commutator store at the incoming varying line rate. A predetermined time later, the stored bits are read out from the commutator-type store and stored in the shift register at a given rate. Finally, the shift register data is read out at a constant predetermined rate. The length of the shift register is controlled by a counter (110). The phase relationship between the commutator write and read cycles is monitored by logic circuitry (501, 502, 503, 504, 505, 506) within the control unit (106). If this phase relationship has increased by a preselected amount, the commutator readout rate is increased along with the length of the shift register. Alternatively, if the phase relationship has decreased by a preselected amount, the commutator store readout rate is decreased along with a decrease of the shift register length.
Inventors
- 👤 Gary A. Turner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 20:43
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06; G06F5/10; H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/062; H04J3/0626; G06F2205/00; G06F2205/06; G06F2205/061
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
246 words
An elastic store for receiving data bits at a variable line rate comprising a first buffer store (102) having a number of storage cells (201, 202, 203, 204), first means (205, 206) for writing in said data bits into said storage cells at said variable line rate, and a second buffer store (104) having a number of addressable storage cells, means for addressing (110) the storage cells in said second buffer, characterized by secod means (513, 514, 515, 516, 517, 518, 519) for reading out said data bits from said first buffer store and writing in said bits into addressed cells in said second buffer store at a given rate, the read-out cycle of said first buffer normally occurring subsequent to the write-in cycle of said first buffer, third means (513, 514, 519, 120) for reading out said data from said second buffer store at a predetermined rate, control means (112) for rendering variable the number of storage cells in said second buffer that are addressed, and first buffer monitor means (501, 502, 503, 504, 506) for examining the phase between the read-out and write-in cycles of said first buffer and producing control signals when the phase drifts by a preselected amount, said control signals causing said given rate to increase or decrease depending upon the relative direction of said drift, said control signals further directing said control means to respectively increase or decrease the number of storage cells in said second buffer that are addressed.
Claim 2
Dependent Claim
246 words
An elastic store for receiving data bits at a variable line rate comprising a first buffer store (102) having a number of storage cells (201, 202, 203, 204), first means (205, 206) for writing in said data bits into said storage cells at said variable line rate, and a second buffer store (104) having a number of addressable storage cells, means for addressing (110) the storage cells in said second buffer, characterized by secod means (513, 514, 515, 516, 517, 518, 519) for reading out said data bits from said first buffer store and writing in said bits into addressed cells in said second buffer store at a given rate, the read-out cycle of said first buffer normally occurring subsequent to the write-in cycle of said first buffer, third means (513, 514, 519, 120) for reading out said data from said second buffer store at a predetermined rate, control means (112) for rendering variable the number of storage cells in said second buffer that are addressed, and first buffer monitor means (501, 502, 503, 504, 506) for examining the phase between the read-out and write-in cycles of said first buffer and producing control signals when the phase drifts by a preselected amount, said control signals causing said given rate to increase or decrease depending upon the relative direction of said drift, said control signals further directing said control means to respectively increase or decrease the number of storage cells in said second buffer that are addressed.
Claim 3
Dependent Claim
25 words
The elastic store of claim 1 wherein the variations in said given rate in response to said control signals drives said first buffer toward half-fill.
Claim 4
Dependent Claim
37 words
The elastic store of claim 1 wherein said preselected amount corresponds to a fill of said first buffer store being a number of bits more than half said number of storage cells of said first buffer store.
Claim 5
Dependent Claim
37 words
The elastic store of claim 1 wherein said preselected amount corresponds to a fill of said first buffer store being a number of bits less than half said number of storage cells of said first buffer store.
Claim 6
Dependent Claim
15 words
The elastic store of claims 3 or 4 wherein said number of bits is one.
Claim 7
Dependent Claim
17 words
The elastic store of claim 5 wherein said second buffer store is a random access memory unit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-04-26 | 1985-10-26 | 1986-04-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-04-26 | 1989-10-26 | 1990-04-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-04-26 | 1993-10-26 | 1994-04-27 | $7700.00 | Window Closed / Lapsed |