Microcomputer with programmable multi-function port

Claim 2

In a microcomputer comprising: a processor; a memory for storing data at selected addresses; a bidirectional data bus comprising a plurality of data lines coupled to the processor and to the memory, for transferring data between the processor and the memory; and an address bus comprising a plurality of address lines coupled to the processor and to the memory, for transferring addresses from the processor to the memory; and a programmable multi-function port for selectively coupling the data and address buses to a plurality of input/output lines, comprising: coupling means coupled to the data bus, the address bus, and the input/output lines, for coupling selected ones of the data lines to respective ones of the input/output lines in response to a first enable signal, for coupling each of the data lines to respective ones of the input/output lines in response to a second enable signal, and for coupling each of the address lines to respective ones of the input/output lines in response to a third enable signal; and mode control means coupled to the coupling means, for selectively providing the first, second and third enable signals.

Claim 3

The microcomputer as recited in claim 1, wherein said mode control means comprises: a mode control register for storing information representing one of the modes of operation of the port, the mode control register being coupled to the coupling means and providing the enable signal corresponding to the mode of operation indicated by the stored information; and means for receiving control signals indicating a desired one of the modes of operation of the port, and for loading said mode control register with information representing the desired mode of operation of said port.

Claim 4

The microcomputer as recited in claim 2, wherein said means for loading said mode control register comprises at least one of the input/output lines of said microcomputer.

Claim 5

A single-chip microcomputer comprising: a processor; an on-chip memory for storing information at selected addresses; an address bus comprising a plurality of address lines coupled to the processor and to the memory, for transferring addresses from the processor to the memory; a bidirectional data bus comprising a plurality of data lines coupled to the processor and to the memory, for transferring data between the processor and the memory; a programmable multi-function port for selectively coupling the data and address lines to a plurality of input/output lines, comprising: coupling means coupled to the address bus, the data bus, and the input/output lines, for coupling selected ones of the input/output lines to respective ones of the data lines in response to a first enable signal, for coupling each of the input/output lines to respective ones of the data lines in response to a second enable signal, and for coupling each of the input/output lines to respective ones of the address lines in response to a third enable signal; control logic coupled to the coupling means, for providing the first enable signal in response to a first mode signal, for providing the second enable signal in response to a second mode signal, and for sequentially providing the third and second enable signals in response to a third mode signal; and means for selectively providing said first mode signal to configure said port as an input/output port in which said input/output lines may be individually programmed as input or output lines, said second mode signal to configure said port as a bidirectional data port, and said third mode signal to configure said port as a multiplexed data/address port.

Claim 6

A single-chip microcomputer comprising: a processor; an on-chip memory for storing information at selected addresses; an address bus comprising a plurality of address lines coupled to the processor and to the memory, for transferring addresses from the processor to the memory; a bidirectional data bus comprising a plurality of data lines coupled to the processor and to the memory, for transferring data between the processor and the memory; a programmable multi-function port for selectively coupling the data and address lines to a plurality of input/output lines, comprising: coupling means coupled to the address bus, the data bus, and the input/output lines, for coupling selected ones of the input/output lines to respective ones of the data lines in response to a first enable signal, for coupling each of the input/output lines to respective ones of the data lines in response to a second enable signal, and for coupling each of the input/output lines to respective ones of the address lines in response to a third enable signal; control logic coupled to the coupling means, for providing the first enable signal in response to a first mode signal, for providing the second enable signal in response to a second mode signal, and for sequentially providing the third and second enable signals in response to a third mode signal; and means for selectively providing said first mode signal to configure said port as an input/output port in which said input/output lines may be individually programmed as input or output lines, said second mode signal to configure said port as a bidirectional data port, and said third mode signal to configure said port as a multiplexed data/address port.

Claim 7

The single-chip microcomputer as recited in claim 4, wherein said means for providing the mode signals are coupled to one or more of said input/output lines, and provide said mode signals in response to predetermined mode control signals applied to said input/output lines.

Claim 8

The single-chip microcomputer as recited in claim 4 wherein the control logic provides, in response to said third mode signal, said third enable signal and thereafter provides said second enable signal only in response to one or more predetermined addresses on said address bus.