Device for increasing the length of a logic computer address

Claim 1

An address generating device for use in a digital data processing system generating a physical address for addressing a segmented random access memory, whereby an increased address length is produced without it being necessary to provide elements within the computer for separate bit slices, said device comprising an instruction register (1) having an input of a predetermined first bit width for a bit string representing an indexed address instruction, said instruction register comprising a first output for an operation code, a second output (5) for selecting an index register from an index register bank (3,4), and a third output (6) for a first relative memory address, wherein the bit width of the index register bank is at least 1.25 and at most said first bit width, said index register bank having a fourth output (7) for outputting a first group of more significant bits therefrom, and a fifth output (8) for outputting a second group of less significant bits therefrom, the second group representing a second relative memory address, said address generating device comprising first adder means (9) for receiving and adding said first and second relative memory addresses to generate on a sixth output (22) thereof a displacement number which in combination with said first group of more significant bits represents a complete logical memory address, wherein said fourth output is connected to an address input of an address segment table (14) memory, each location thereof accomodating a segment base identification to be outputted on a seventh output (19) thereof having a bit width that is at least equal to said first bit width and at most 1.5 times than said address bit width, said address generating device furthermore comprising output adding means receiving from said sixth and seventh outputs the logical memory address and segment base indentification and having an eighth output for thereon outputting an absolute address for said memory.