US4371962A
Expired / Lapsed
US
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Circuit arrangement for compensating phase differences of non-synchronous clock pulse rates of a telecommunication system
Assignee: Siemens AG
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Filing: 1980-09-08
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Granted: 1983-02-01
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Expires: 2000-09-08
Abstract
Abstract A pulse coded time division multiplex (PCM) telecommunication system has two non-synchronous clock pulse trains for controlling information transfer and switching operations, respectively. In a circuit arrangement for compensating phase differences resulting from deviations between both clock pulse trains there is arranged an intermediate store for externally controlled buffering of PCM words for half of a pulse frame and connected thereto a buffer store for internally controlled buffering of PCM words for a full pulse frame. The intermediate store is designed for two modes of operation under control of the external clock pulse train. In an active mode during one cycle at first a stored PCM word is read out and is then replaced by a new PCM word. In the second mode the same PCM word first is temporarily buffered and immediately read out thereafter. Change of operation is controlled by a control unit monitoring addresses for alternate read operations and write operations of the buffer store of a minimum off-set of selected addresses to obtain by skipping of half of a pulse frame sufficient off-set without continuous uncontrolled slippage losses.
Inventors
- 👤 Rolf Zeitraeg
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:23
CPC Classifications
H; H04; H04Q; H04Q11/00; H04Q11/04; H04Q11/08; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/062; H04J3/0626
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
428 words
Circuit arrangement for a pulse coded time division multiplex (PCM) telecommunication system for compensating phase differences resulting from deviations between rates of an external clock pulse train controlling transmission of information across an incoming transmission line and of a non-synchronous internal clock pulse train controlling switching operations of an exchange, said circuit arrangement being arranged between said incoming transmission line for serial transmission of PCM information and an outgoing transmission line connected to the exchange for parallel transmission of PCM words which correspond to PCM information sampled from one speech channel and being transferred in one channel time slot, comprising: (a) first storage means for consecutively storing PCM words for half of a pulse frame and having parallel data inputs and respective data outputs for one PCM word, said first storage means being designed for two modes of operation, wherein during one channel time slot defined by said external clock pulse train in an active mode of operation at first a stored PCM word is read out from a selected storage location and then a new PCM word separated from the previously stored PCM word by a half of a pulse frame is written in, and in a non-active mode the same PCM word first is temporarily buffered and read out thereafter; (b) an intermediate register having a capacity for one PCM word and for a binary coded channel address, and having corresponding parallel data inputs and outputs, and parallel address inputs and outputs, said data inputs being connected in parallel with respective ones of said data outputs of said first storage means; (c) second storage means for consecutively storing PCM words of a full pulse frame under control of said internal clock pulse train and having parallel data inputs connected to said data outputs of said intermediate register, having data outputs connected to said outgoing transmission line and having address inputs; (d) means for generating consecutive binary coded channel addresses of an entire pulse frame under control of said external clock pulse train and having parallel address outputs for channel address bits and connected in parallel with both respective address inputs of said first storage means and address inputs of said intermediate register; and (e) control means for determining the mode of operation of said first storage means dependent upon a minimum off-set of read addresses and write addresses for the second storage means, wherein the mode of operation of the first storage means is changed and the most significant bit of a full channel address is inverted whenever the current offset is lower than said minimum.
Claim 2
Dependent Claim
428 words
Circuit arrangement for a pulse coded time division multiplex (PCM) telecommunication system for compensating phase differences resulting from deviations between rates of an external clock pulse train controlling transmission of information across an incoming transmission line and of a non-synchronous internal clock pulse train controlling switching operations of an exchange, said circuit arrangement being arranged between said incoming transmission line for serial transmission of PCM information and an outgoing transmission line connected to the exchange for parallel transmission of PCM words which correspond to PCM information sampled from one speech channel and being transferred in one channel time slot, comprising: (a) first storage means for consecutively storing PCM words for half of a pulse frame and having parallel data inputs and respective data outputs for one PCM word, said first storage means being designed for two modes of operation, wherein during one channel time slot defined by said external clock pulse train in an active mode of operation at first a stored PCM word is read out from a selected storage location and then a new PCM word separated from the previously stored PCM word by a half of a pulse frame is written in, and in a non-active mode the same PCM word first is temporarily buffered and read out thereafter; (b) an intermediate register having a capacity for one PCM word and for a binary coded channel address, and having corresponding parallel data inputs and outputs, and parallel address inputs and outputs, said data inputs being connected in parallel with respective ones of said data outputs of said first storage means; (c) second storage means for consecutively storing PCM words of a full pulse frame under control of said internal clock pulse train and having parallel data inputs connected to said data outputs of said intermediate register, having data outputs connected to said outgoing transmission line and having address inputs; (d) means for generating consecutive binary coded channel addresses of an entire pulse frame under control of said external clock pulse train and having parallel address outputs for channel address bits and connected in parallel with both respective address inputs of said first storage means and address inputs of said intermediate register; and (e) control means for determining the mode of operation of said first storage means dependent upon a minimum off-set of read addresses and write addresses for the second storage means, wherein the mode of operation of the first storage means is changed and the most significant bit of a full channel address is inverted whenever the current offset is lower than said minimum.
Claim 3
Dependent Claim
136 words
The circuit arrangement as recited in claim 1, further comprising: (f) means for generating consecutive read addresses for the second storage means under control of the internal clock pulse train having a clock pulse input supplied with said clock pulses and parallel address outputs; and (g) read/write control means for controlling storage operations of the second storage means having first address inputs connected to the address outputs of the intermediate register for receiving a write address and second address inputs connected to said address outputs of said means for generating read addresses, having control means for alternately switching read address and a write address to address inputs of said second storage means and having enabling means for starting alternately a read operation and a write operation in said second storage means within one channel time slot.
Claim 4
Dependent Claim
83 words
The circuit arrangement as recited in claim 2, further comprising a further intermediate register having a storage capacity of one PCM word and having corresponding parallel data inputs and data outputs and a clock input, said data outputs being connected in parallel to respective data inputs of the first storage means for transferring a PCM word into said first storage means under control of a transfer pulse derived from the external clock pulse train occurring in the middle of the channel time slot.
Claim 5
Dependent Claim
57 words
The circuit arrangement as recited in claim 3, further comprising an input shift register controlled by the external clock pulse train, having a serial input coupled to the incoming transmission line and having parallel outputs connected in parallel to both data inputs of said further intermediate register and data inputs of the means for generating channel addresses.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-01-31 | 1986-08-02 | 1987-02-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-01-31 | 1990-08-02 | 1991-02-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-01-31 | 1994-08-02 | 1995-02-01 | $7700.00 | Window Closed / Lapsed |