US4379238A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated signal processing circuit
Assignee: Panasonic Holdings Corp
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Filing: 1982-02-26
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Granted: 1983-04-05
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Expires: 2002-02-26
Abstract
Abstract Disclosed is an integrated circuit in which more than two kinds of information outputs are superimposed on the same output terminal and the output level of an output terminal is varied in more than three steps in order to apply many information outputs to a small number of output terminals and transmit the operation state of the internal circuit externally. The structure of the integrated circuit is simplified, because the number of terminals in the integrated circuit and the number of connection wires between internal and external circuits can be reduced.
Inventors
- 👤 Hiroshi Minakuchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 18:05
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/60; H03K17/62; H03K17/6242
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
199 words
An integrated signal processing circuit for transmitting externally a plurality of output signals over a signal output path comprising: a first input signal path for receiving a first output signal which varies between at least two D.C. levels; a second input signal path for receiving a second output signal having a pulse width shorter than the period of level variation of said first output signal; a mixing circuit coupled to said first and second input signal paths for synthesizing a composite output from said first and second output signals, said mixing circuit inverting the phase of said second output signal and transmitting it to said signal output path when said first output signal has a first level and transmitting said second output signal to said signal output path without inversion when said first output signal has a second level, said mixing circuit comprising a first AND gate having input terminals receiving said first output signal and a phase inverted said second output signal, a second AND gate having input terminals receiving a phase inverted first output signal and said second output signal, and an OR gate having input terminals receiving output signals from said first and second AND gates.
Claim 2
Dependent Claim
199 words
An integrated signal processing circuit for transmitting externally a plurality of output signals over a signal output path comprising: a first input signal path for receiving a first output signal which varies between at least two D.C. levels; a second input signal path for receiving a second output signal having a pulse width shorter than the period of level variation of said first output signal; a mixing circuit coupled to said first and second input signal paths for synthesizing a composite output from said first and second output signals, said mixing circuit inverting the phase of said second output signal and transmitting it to said signal output path when said first output signal has a first level and transmitting said second output signal to said signal output path without inversion when said first output signal has a second level, said mixing circuit comprising a first AND gate having input terminals receiving said first output signal and a phase inverted said second output signal, a second AND gate having input terminals receiving a phase inverted first output signal and said second output signal, and an OR gate having input terminals receiving output signals from said first and second AND gates.
Claim 3
Dependent Claim
198 words
An integrated signal processing circuit for transmitting externally a plurality of digital information output signals over a signal output path comprising: a first input signal path for receiving a first digital information output signal which varies stepwise between two D.C. levels; a second input signal path for receiving a second digital information output signal having a pulse width shorter than the period of level variation of said first digital information output signal, and which varies stepwise between said two D.C. levels; and a mixing circuit coupled to said first and second input signal paths for synthesizing a composite output signal including said first and second digital information output signals, said mixing circuit including means for transmitting a first D.C. level higher or lower than a voltage division level and a third D.C. level lower or higher than said voltage division level to a signal output terminal in accordance with said digital information output signals, said composite output signal having an envelope which varies between said first and second D.C. levels according to the state of said first digital information output signal and reaching said third D.C. level in response to changes in said second digital information output signal.
Claim 4
Dependent Claim
198 words
An integrated signal processing circuit for transmitting externally a plurality of digital information output signals over a signal output path comprising: a first input signal path for receiving a first digital information output signal which varies stepwise between two D.C. levels; a second input signal path for receiving a second digital information output signal having a pulse width shorter than the period of level variation of said first digital information output signal, and which varies stepwise between said two D.C. levels; and a mixing circuit coupled to said first and second input signal paths for synthesizing a composite output signal including said first and second digital information output signals, said mixing circuit including means for transmitting a first D.C. level higher or lower than a voltage division level and a third D.C. level lower or higher than said voltage division level to a signal output terminal in accordance with said digital information output signals, said composite output signal having an envelope which varies between said first and second D.C. levels according to the state of said first digital information output signal and reaching said third D.C. level in response to changes in said second digital information output signal.
Claim 5
Dependent Claim
71 words
An integrated signal processing circuit according to claim 2, wherein said mixing circuit comprises: a first switching transistor which supplies said signal output terminal with said second D.C. level when said first input signal path has a predetermined signal level applied thereto; and a second switching transistor which supplies said signal output terminal with said third D.C. level when said second input signal path has a predetermined signal level applied thereto.
Claim 6
Dependent Claim
175 words
An integrated signal processing circuit for transmitting externally a composite output signal including, an analogue information and a digital information over a signal output path comprising: a first input signal path for receiving an analogue information output signal which varies between two D.C. levels; a second input signal path for receiving a digital information output signal which varies stepwise between said two D.C. levels; and a mixing circuit coupled to said first and second input signal paths for synthesizing said composite output signal, said mixing circuit comprising, a first transistor which supplies said signal output terminal with said analogue information output signal, and a second switching transistor which supplies said signal output terminal with a third D.C. level when said second input signal path has a predetermined signal level applied thereto, said composite output signal having a first portion which varies between said two D.C. levels in accordance with said analogue information output signal and a second portion which reaches said third D.C. level when said digital information output signal has said predetermined signal level.
Claim 7
Dependent Claim
175 words
An integrated signal processing circuit for transmitting externally a composite output signal including, an analogue information and a digital information over a signal output path comprising: a first input signal path for receiving an analogue information output signal which varies between two D.C. levels; a second input signal path for receiving a digital information output signal which varies stepwise between said two D.C. levels; and a mixing circuit coupled to said first and second input signal paths for synthesizing said composite output signal, said mixing circuit comprising, a first transistor which supplies said signal output terminal with said analogue information output signal, and a second switching transistor which supplies said signal output terminal with a third D.C. level when said second input signal path has a predetermined signal level applied thereto, said composite output signal having a first portion which varies between said two D.C. levels in accordance with said analogue information output signal and a second portion which reaches said third D.C. level when said digital information output signal has said predetermined signal level.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-04-04 | 1986-10-04 | 1987-04-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-04-04 | 1990-10-04 | 1991-04-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-04-04 | 1994-10-04 | 1995-04-05 | $7700.00 | Window Closed / Lapsed |