High density electrically erasable floating gate dual-injection programmable memory device

Claim 3

A method according to claim 1, wherein said charge-storage level is a floating gate which is charged by electrons injected through a dielectric layer between said source-drain path and the floating gate and erased by holes injected through said dielectric layer.

Claim 4

A method according to claim 1 including the step of applying an electrically floating condition to the other and the source-drain path of said selected cell.

Claim 5

A method according to claim 1, wherein said erase voltage and said high voltage are greater than a programming voltage level for said cells.

Claim 6

A method according to claim 4 wherein said erase voltage produces avalanche breakdown at said one end of the source-drain path.

Claim 7

A method according to claim 5, wherein said high voltage raises the avalanche breakdown voltage of said non-selected cells to higher than said erase voltage.

Claim 10

A method according to claim 7, wherein the columns other than said selected column are floating.

Claim 11

A method according to claim 7, wherein the columns other than said selected column are at a voltage higher than said low voltage but lower than said high voltage.

Claim 12

A method according to claim 7, wherein said avalanche voltage is greater than a programming voltage for said transistors.

Claim 13

A method according to claim 10, wherein said low voltage is ground.

Claim 14

An electrically erasable floating gate type semiconductor memory array comprising: a plurality of field-effect transistor devices each having a source, a drain, a floating gate, and a control gate, the floating gate being isolated from the channel between source and drain by thin insulator and the control gate being isolated from the floating gate by thin insulator, the transistor devices being arranged in array of rows and columns, with the columns of transistor devices being the sources and drains connected to elongated parallel column lines; means connecting the control gates of all devices in each row together to provide row lines; said memory array functioning to read out logic-level voltage by selective application of logic-level voltage on the column lines and row lines; and erasing means comprising: means for applying an erase voltage to a selected one of the column lines; means for applying a high voltage to all said row lines except a selected row line; and means for applying a low voltage to said selected row line; said erase voltage and said high voltage being higher than said logic-level voltage, and said low voltage being lower than said high voltage.

Claim 15

An electrically erasable floating gate type semiconductor memory array comprising: a plurality of field-effect transistor devices each having a source, a drain, a floating gate, and a control gate, the floating gate being isolated from the channel between source and drain by thin insulator and the control gate being isolated from the floating gate by thin insulator, the transistor devices being arranged in array of rows and columns, with the columns of transistor devices being the sources and drains connected to elongated parallel column lines; means connecting the control gates of all devices in each row together to provide row lines; said memory array functioning to read out logic-level voltage by selective application of logic-level voltage on the column lines and row lines; and erasing means comprising: means for applying an erase voltage to a selected one of the column lines; means for applying a high voltage to all said row lines except a selected row line; and means for applying a low voltage to said selected row line; said erase voltage and said high voltage being higher than said logic-level voltage, and said low voltage being lower than said high voltage.

Claim 16

A memory array according to claim 12, wherein said erase voltage produces avalanche breakdown in the transistor device in said selected row and selected column but in no other transistor devices in said array.

Claim 17

A memory array according to claim 13 wherein the avalanche breakdown of transistor devices in all rows except said selected row is raised to a higher level by said high voltage.

Claim 18

A memory array according to claim 14, wherein the transistor devices are N-channel and the floating gates and control gates are separate layers of polycrystalline silicon.

Claim 19

A memory array according to claim 14 wherein said column lines other than said selected one are electrically floating.

Claim 22

A method according to claim 17 wherein said floating gate is erased by holes injected through a dielectric layer between said source-drain path and the floating gate when the transistor is in avalanche condition.

Claim 23

A method according to claim 18 wherein the time of first applying said low voltage to the control gate is after the time of first applying said avalanche voltage to the source-drain path.

Claim 24

A method according to claim 19 wherein a plurality of said cells are included in an array of rows and columns, and each column has a plurality of source-drain paths of cells connected between such column and a parallel column, and said step of applying avalanche voltage uses such column as a conductor.

Claim 25

A method according to claim 20 wherein each row is connected to said control gates of a plurality of said cells, and the step of applying a low voltages uses a row as a conductor.

Claim 26

A method according to claim 21 wherein said high potential and said avalanche voltage are much greater than threshold voltage for the cell.

Claim 27

An electrically erasable, electrically programmable semiconductor memory device comprising: an array of rows and columns of memory cells, each cell having a control gate connected by a row line to control gates of all cells in a row, each cell having a source-drain path connected to its ends to adjacent column lines, a floating gate between said source-drain path and control gate in each cell; the memory device functioning to read out logic-level voltage from the memory cells by selective application of logic-level voltage to the row and column lines; means for charging the capacitance of a selected one of the column lines to an erase voltage greater than said logic-level voltage over a time interval; means for maintaining the control gates of all cells in the array at a high level voltage greater than said logic-level voltage causing the source-drain paths to be in a non-erase condition during said time interval; and means for connecting a selected one of said row lines to a lower voltage at a time beginning after said time interval to cause discharging of the floating gate of one of the cells by carrier injection; said lower voltage being substantially less than said high level voltage.

Claim 28

An electrically erasable, electrically programmable semiconductor memory device comprising: an array of rows and columns of memory cells, each cell having a control gate connected by a row line to control gates of all cells in a row, each cell having a source-drain path connected to its ends to adjacent column lines, a floating gate between said source-drain path and control gate in each cell; the memory device functioning to read out logic-level voltage from the memory cells by selective application of logic-level voltage to the row and column lines; means for charging the capacitance of a selected one of the column lines to an erase voltage greater than said logic-level voltage over a time interval; means for maintaining the control gates of all cells in the array at a high level voltage greater than said logic-level voltage causing the source-drain paths to be in a non-erase condition during said time interval; and means for connecting a selected one of said row lines to a lower voltage at a time beginning after said time interval to cause discharging of the floating gate of one of the cells by carrier injection; said lower voltage being substantially less than said high level voltage.

Claim 29

A device according to claim 23 wherein said erase voltage and said high level both are much higher than the threshold voltage which turns on the source-drain path in a normal read operation.

Claim 30

A device according to claim 24 wherein said erase voltage is higher than a programming voltage for said cells.

Claim 31

A device according to claim 25 wherein means are connected to said column lines for coupling a column line adjacent said selected one to reference potential or to a floating condition.

Claim 32

A device according to claim 26 wherein said time interval is much greater than the cycle time of a normal read operation.